Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1104991887	165140	0	0
ctrl_regwen_rd_A	1104991887	8208	0	0
exec_rd_A	1104991887	8036	0	0
exec_regwen_rd_A	1104991887	8567	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104991887	165140	0	0
T13	235874	0	0	0
T15	106766	0	0	0
T25	217269	0	0	0
T26	433551	0	0	0
T30	30536	689	0	0
T31	30107	1465	0	0
T32	0	1881	0	0
T33	34708	0	0	0
T50	0	1836	0	0
T51	0	6022	0	0
T52	0	3627	0	0
T53	0	618	0	0
T54	0	6284	0	0
T55	0	4158	0	0
T56	0	7774	0	0
T57	232648	0	0	0
T58	76677	0	0	0
T59	197859	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104991887	8208	0	0
T6	255060	0	0	0
T17	173460	0	0	0
T19	1140	0	0	0
T32	62431	473	0	0
T34	33711	0	0	0
T47	182584	0	0	0
T98	189738	0	0	0
T99	374480	0	0	0
T108	0	837	0	0
T109	0	213	0	0
T110	0	421	0	0
T111	0	230	0	0
T112	0	824	0	0
T113	0	105	0	0
T114	0	891	0	0
T115	0	127	0	0
T116	0	164	0	0
T117	77643	0	0	0
T118	173940	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104991887	8036	0	0
T6	255060	0	0	0
T17	173460	0	0	0
T19	1140	0	0	0
T32	62431	402	0	0
T34	33711	0	0	0
T47	182584	0	0	0
T98	189738	0	0	0
T99	374480	0	0	0
T108	0	719	0	0
T109	0	156	0	0
T110	0	381	0	0
T111	0	206	0	0
T112	0	784	0	0
T113	0	116	0	0
T114	0	812	0	0
T115	0	198	0	0
T116	0	207	0	0
T117	77643	0	0	0
T118	173940	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1104991887	8567	0	0
T6	255060	0	0	0
T17	173460	0	0	0
T19	1140	0	0	0
T32	62431	366	0	0
T34	33711	0	0	0
T47	182584	0	0	0
T98	189738	0	0	0
T99	374480	0	0	0
T108	0	967	0	0
T109	0	211	0	0
T110	0	364	0	0
T111	0	245	0	0
T112	0	777	0	0
T113	0	111	0	0
T114	0	871	0	0
T115	0	208	0	0
T116	0	179	0	0
T117	77643	0	0	0
T118	173940	0	0	0