Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.41 100.00 97.91 100.00 100.00 99.72 99.70 98.52


Total test records in report: 1037
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html

T317 /workspace/coverage/default/46.sram_ctrl_mem_partial_access.3683678049 Mar 14 12:54:23 PM PDT 24 Mar 14 12:55:33 PM PDT 24 2360369911 ps
T318 /workspace/coverage/default/12.sram_ctrl_mem_partial_access.646909138 Mar 14 12:51:06 PM PDT 24 Mar 14 12:52:19 PM PDT 24 7156361662 ps
T319 /workspace/coverage/default/27.sram_ctrl_partial_access.646931612 Mar 14 12:51:54 PM PDT 24 Mar 14 12:52:04 PM PDT 24 1279222805 ps
T320 /workspace/coverage/default/4.sram_ctrl_ram_cfg.142218987 Mar 14 12:50:35 PM PDT 24 Mar 14 12:50:38 PM PDT 24 475669612 ps
T321 /workspace/coverage/default/45.sram_ctrl_mem_walk.3952725077 Mar 14 12:54:17 PM PDT 24 Mar 14 12:56:23 PM PDT 24 8218854787 ps
T322 /workspace/coverage/default/44.sram_ctrl_max_throughput.135330472 Mar 14 12:54:01 PM PDT 24 Mar 14 12:54:45 PM PDT 24 732469189 ps
T323 /workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2822232866 Mar 14 12:50:53 PM PDT 24 Mar 14 12:53:07 PM PDT 24 1797361285 ps
T324 /workspace/coverage/default/14.sram_ctrl_throughput_w_partial_write.1867240248 Mar 14 12:51:09 PM PDT 24 Mar 14 12:51:43 PM PDT 24 1612517204 ps
T325 /workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.926467553 Mar 14 12:50:26 PM PDT 24 Mar 14 12:50:32 PM PDT 24 836898208 ps
T326 /workspace/coverage/default/44.sram_ctrl_regwen.1286454420 Mar 14 12:54:05 PM PDT 24 Mar 14 12:59:33 PM PDT 24 18849663515 ps
T327 /workspace/coverage/default/41.sram_ctrl_mem_partial_access.1752597962 Mar 14 12:53:43 PM PDT 24 Mar 14 12:54:59 PM PDT 24 2461318752 ps
T328 /workspace/coverage/default/46.sram_ctrl_partial_access.478722884 Mar 14 12:54:27 PM PDT 24 Mar 14 12:54:38 PM PDT 24 2367531831 ps
T329 /workspace/coverage/default/4.sram_ctrl_smoke.2636313117 Mar 14 12:50:46 PM PDT 24 Mar 14 12:51:16 PM PDT 24 4073723647 ps
T330 /workspace/coverage/default/9.sram_ctrl_smoke.192160381 Mar 14 12:50:54 PM PDT 24 Mar 14 12:51:40 PM PDT 24 1681688597 ps
T331 /workspace/coverage/default/21.sram_ctrl_lc_escalation.1825880463 Mar 14 12:51:22 PM PDT 24 Mar 14 12:51:34 PM PDT 24 1884494375 ps
T332 /workspace/coverage/default/2.sram_ctrl_stress_all.3515693968 Mar 14 12:50:37 PM PDT 24 Mar 14 02:22:30 PM PDT 24 138897926580 ps
T333 /workspace/coverage/default/45.sram_ctrl_stress_pipeline.3368764303 Mar 14 12:54:16 PM PDT 24 Mar 14 12:58:01 PM PDT 24 4478741864 ps
T334 /workspace/coverage/default/7.sram_ctrl_partial_access_b2b.2028210442 Mar 14 12:50:53 PM PDT 24 Mar 14 12:56:18 PM PDT 24 26391550864 ps
T335 /workspace/coverage/default/22.sram_ctrl_access_during_key_req.1836306517 Mar 14 12:51:19 PM PDT 24 Mar 14 01:01:45 PM PDT 24 10296163386 ps
T336 /workspace/coverage/default/8.sram_ctrl_ram_cfg.1065585389 Mar 14 12:50:53 PM PDT 24 Mar 14 12:50:56 PM PDT 24 352025664 ps
T337 /workspace/coverage/default/5.sram_ctrl_access_during_key_req.2674416729 Mar 14 12:50:38 PM PDT 24 Mar 14 01:04:52 PM PDT 24 9101728276 ps
T338 /workspace/coverage/default/26.sram_ctrl_executable.1626498959 Mar 14 12:51:48 PM PDT 24 Mar 14 01:05:19 PM PDT 24 9597146295 ps
T339 /workspace/coverage/default/47.sram_ctrl_mem_walk.2248377137 Mar 14 12:54:49 PM PDT 24 Mar 14 12:59:54 PM PDT 24 68909472992 ps
T340 /workspace/coverage/default/49.sram_ctrl_mem_partial_access.1385459776 Mar 14 12:54:59 PM PDT 24 Mar 14 12:56:23 PM PDT 24 2729715061 ps
T341 /workspace/coverage/default/24.sram_ctrl_stress_all.2129335145 Mar 14 12:51:45 PM PDT 24 Mar 14 01:52:52 PM PDT 24 111168243561 ps
T342 /workspace/coverage/default/23.sram_ctrl_throughput_w_partial_write.1007222072 Mar 14 12:51:36 PM PDT 24 Mar 14 12:51:43 PM PDT 24 680112123 ps
T343 /workspace/coverage/default/0.sram_ctrl_executable.3945199606 Mar 14 12:50:37 PM PDT 24 Mar 14 01:07:07 PM PDT 24 6763874601 ps
T344 /workspace/coverage/default/21.sram_ctrl_multiple_keys.1099918740 Mar 14 12:51:16 PM PDT 24 Mar 14 01:00:00 PM PDT 24 14358886833 ps
T345 /workspace/coverage/default/42.sram_ctrl_lc_escalation.4017666088 Mar 14 12:53:54 PM PDT 24 Mar 14 12:54:52 PM PDT 24 19494821675 ps
T346 /workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3209525738 Mar 14 12:51:02 PM PDT 24 Mar 14 12:51:17 PM PDT 24 1084761948 ps
T84 /workspace/coverage/default/6.sram_ctrl_mem_partial_access.1893925665 Mar 14 12:50:49 PM PDT 24 Mar 14 12:52:05 PM PDT 24 5443664491 ps
T347 /workspace/coverage/default/9.sram_ctrl_access_during_key_req.841585266 Mar 14 12:50:53 PM PDT 24 Mar 14 12:55:53 PM PDT 24 17328701309 ps
T348 /workspace/coverage/default/0.sram_ctrl_ram_cfg.574771321 Mar 14 12:50:30 PM PDT 24 Mar 14 12:50:33 PM PDT 24 683407032 ps
T349 /workspace/coverage/default/3.sram_ctrl_throughput_w_partial_write.2298877036 Mar 14 12:50:34 PM PDT 24 Mar 14 12:53:03 PM PDT 24 3114588432 ps
T350 /workspace/coverage/default/25.sram_ctrl_max_throughput.4231974607 Mar 14 12:51:42 PM PDT 24 Mar 14 12:52:00 PM PDT 24 729590403 ps
T351 /workspace/coverage/default/32.sram_ctrl_ram_cfg.3403761737 Mar 14 12:52:38 PM PDT 24 Mar 14 12:52:41 PM PDT 24 2517134918 ps
T352 /workspace/coverage/default/41.sram_ctrl_throughput_w_partial_write.2794069103 Mar 14 12:53:45 PM PDT 24 Mar 14 12:53:52 PM PDT 24 1373732507 ps
T353 /workspace/coverage/default/3.sram_ctrl_max_throughput.2563108189 Mar 14 12:50:45 PM PDT 24 Mar 14 12:51:16 PM PDT 24 715616199 ps
T354 /workspace/coverage/default/2.sram_ctrl_executable.930561666 Mar 14 12:50:28 PM PDT 24 Mar 14 12:51:56 PM PDT 24 6160707457 ps
T355 /workspace/coverage/default/14.sram_ctrl_executable.1858223334 Mar 14 12:51:10 PM PDT 24 Mar 14 12:52:17 PM PDT 24 20090831400 ps
T356 /workspace/coverage/default/3.sram_ctrl_access_during_key_req.4093263658 Mar 14 12:50:28 PM PDT 24 Mar 14 01:11:36 PM PDT 24 70145498443 ps
T357 /workspace/coverage/default/46.sram_ctrl_executable.3275389183 Mar 14 12:54:23 PM PDT 24 Mar 14 01:02:10 PM PDT 24 12803846445 ps
T358 /workspace/coverage/default/8.sram_ctrl_regwen.1525524333 Mar 14 12:50:55 PM PDT 24 Mar 14 01:00:22 PM PDT 24 8388733594 ps
T359 /workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.3773934591 Mar 14 12:51:50 PM PDT 24 Mar 14 12:52:05 PM PDT 24 572809696 ps
T360 /workspace/coverage/default/21.sram_ctrl_smoke.18710358 Mar 14 12:51:10 PM PDT 24 Mar 14 12:51:29 PM PDT 24 7305997348 ps
T361 /workspace/coverage/default/42.sram_ctrl_regwen.3359679654 Mar 14 12:53:52 PM PDT 24 Mar 14 01:11:14 PM PDT 24 68966327254 ps
T362 /workspace/coverage/default/33.sram_ctrl_mem_walk.2374470541 Mar 14 12:52:39 PM PDT 24 Mar 14 12:55:27 PM PDT 24 30903875083 ps
T363 /workspace/coverage/default/23.sram_ctrl_max_throughput.2347714806 Mar 14 12:51:30 PM PDT 24 Mar 14 12:53:29 PM PDT 24 12630326036 ps
T364 /workspace/coverage/default/47.sram_ctrl_partial_access.2801346277 Mar 14 12:54:37 PM PDT 24 Mar 14 12:54:42 PM PDT 24 1481711345 ps
T365 /workspace/coverage/default/5.sram_ctrl_partial_access.3159624883 Mar 14 12:50:48 PM PDT 24 Mar 14 12:51:02 PM PDT 24 2258279588 ps
T366 /workspace/coverage/default/13.sram_ctrl_stress_pipeline.1963325160 Mar 14 12:51:07 PM PDT 24 Mar 14 12:57:31 PM PDT 24 10818965976 ps
T367 /workspace/coverage/default/27.sram_ctrl_mem_partial_access.3746685202 Mar 14 12:51:54 PM PDT 24 Mar 14 12:53:06 PM PDT 24 2478320629 ps
T368 /workspace/coverage/default/29.sram_ctrl_throughput_w_partial_write.2343966523 Mar 14 12:52:04 PM PDT 24 Mar 14 12:54:19 PM PDT 24 1597665516 ps
T369 /workspace/coverage/default/38.sram_ctrl_mem_walk.4201764904 Mar 14 12:53:15 PM PDT 24 Mar 14 12:55:42 PM PDT 24 28703107376 ps
T370 /workspace/coverage/default/46.sram_ctrl_stress_all.3640942098 Mar 14 12:54:38 PM PDT 24 Mar 14 01:46:45 PM PDT 24 50799733571 ps
T371 /workspace/coverage/default/44.sram_ctrl_stress_pipeline.3087245656 Mar 14 12:54:03 PM PDT 24 Mar 14 12:58:06 PM PDT 24 6762131891 ps
T372 /workspace/coverage/default/9.sram_ctrl_multiple_keys.1925022611 Mar 14 12:51:07 PM PDT 24 Mar 14 12:53:55 PM PDT 24 10187018713 ps
T373 /workspace/coverage/default/29.sram_ctrl_ram_cfg.949485898 Mar 14 12:52:17 PM PDT 24 Mar 14 12:52:20 PM PDT 24 720883111 ps
T374 /workspace/coverage/default/28.sram_ctrl_ram_cfg.700863795 Mar 14 12:52:04 PM PDT 24 Mar 14 12:52:08 PM PDT 24 1301694662 ps
T375 /workspace/coverage/default/11.sram_ctrl_lc_escalation.1416846027 Mar 14 12:51:06 PM PDT 24 Mar 14 12:52:01 PM PDT 24 8609754144 ps
T376 /workspace/coverage/default/49.sram_ctrl_partial_access.2719933838 Mar 14 12:54:59 PM PDT 24 Mar 14 12:55:33 PM PDT 24 1559845586 ps
T377 /workspace/coverage/default/12.sram_ctrl_lc_escalation.3114114192 Mar 14 12:51:05 PM PDT 24 Mar 14 12:52:07 PM PDT 24 12526072049 ps
T109 /workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3165204247 Mar 14 12:52:45 PM PDT 24 Mar 14 12:52:57 PM PDT 24 501446735 ps
T378 /workspace/coverage/default/1.sram_ctrl_bijection.2473966461 Mar 14 12:50:31 PM PDT 24 Mar 14 01:29:46 PM PDT 24 132214715612 ps
T379 /workspace/coverage/default/27.sram_ctrl_alert_test.870844882 Mar 14 12:51:56 PM PDT 24 Mar 14 12:51:57 PM PDT 24 37249364 ps
T380 /workspace/coverage/default/33.sram_ctrl_stress_all.3669766132 Mar 14 12:52:41 PM PDT 24 Mar 14 01:48:40 PM PDT 24 135293397548 ps
T381 /workspace/coverage/default/11.sram_ctrl_access_during_key_req.3884095576 Mar 14 12:51:06 PM PDT 24 Mar 14 01:09:09 PM PDT 24 203275162107 ps
T382 /workspace/coverage/default/10.sram_ctrl_alert_test.2861176370 Mar 14 12:50:55 PM PDT 24 Mar 14 12:50:55 PM PDT 24 13245385 ps
T383 /workspace/coverage/default/31.sram_ctrl_mem_partial_access.1968043533 Mar 14 12:52:27 PM PDT 24 Mar 14 12:53:37 PM PDT 24 2369503193 ps
T384 /workspace/coverage/default/39.sram_ctrl_partial_access_b2b.3654152747 Mar 14 12:53:24 PM PDT 24 Mar 14 12:58:03 PM PDT 24 14024638014 ps
T385 /workspace/coverage/default/38.sram_ctrl_lc_escalation.3303081754 Mar 14 12:53:14 PM PDT 24 Mar 14 12:53:35 PM PDT 24 15642848246 ps
T386 /workspace/coverage/default/4.sram_ctrl_max_throughput.2154389029 Mar 14 12:50:45 PM PDT 24 Mar 14 12:52:22 PM PDT 24 772703855 ps
T387 /workspace/coverage/default/28.sram_ctrl_mem_partial_access.4054740387 Mar 14 12:52:06 PM PDT 24 Mar 14 12:53:18 PM PDT 24 948506525 ps
T388 /workspace/coverage/default/30.sram_ctrl_multiple_keys.2660880074 Mar 14 12:52:13 PM PDT 24 Mar 14 01:01:32 PM PDT 24 33494454126 ps
T389 /workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3149431030 Mar 14 12:53:35 PM PDT 24 Mar 14 12:55:26 PM PDT 24 1882097891 ps
T390 /workspace/coverage/default/49.sram_ctrl_mem_walk.597130001 Mar 14 12:55:00 PM PDT 24 Mar 14 12:57:42 PM PDT 24 12035995872 ps
T391 /workspace/coverage/default/2.sram_ctrl_mem_partial_access.2974222528 Mar 14 12:50:33 PM PDT 24 Mar 14 12:53:12 PM PDT 24 9719369741 ps
T392 /workspace/coverage/default/10.sram_ctrl_max_throughput.1314708744 Mar 14 12:50:58 PM PDT 24 Mar 14 12:51:12 PM PDT 24 2158141790 ps
T393 /workspace/coverage/default/8.sram_ctrl_partial_access_b2b.2497788357 Mar 14 12:51:06 PM PDT 24 Mar 14 12:57:53 PM PDT 24 39433342144 ps
T394 /workspace/coverage/default/9.sram_ctrl_stress_pipeline.632799593 Mar 14 12:51:02 PM PDT 24 Mar 14 12:55:52 PM PDT 24 24264992548 ps
T395 /workspace/coverage/default/13.sram_ctrl_multiple_keys.2214575505 Mar 14 12:51:03 PM PDT 24 Mar 14 12:58:51 PM PDT 24 42853063633 ps
T396 /workspace/coverage/default/32.sram_ctrl_smoke.339150159 Mar 14 12:52:28 PM PDT 24 Mar 14 12:52:38 PM PDT 24 680848368 ps
T110 /workspace/coverage/default/15.sram_ctrl_stress_all_with_rand_reset.369055993 Mar 14 12:51:10 PM PDT 24 Mar 14 12:51:51 PM PDT 24 1386880611 ps
T397 /workspace/coverage/default/32.sram_ctrl_multiple_keys.2857631946 Mar 14 12:52:27 PM PDT 24 Mar 14 01:12:55 PM PDT 24 29142206748 ps
T398 /workspace/coverage/default/3.sram_ctrl_mem_partial_access.1969321291 Mar 14 12:50:34 PM PDT 24 Mar 14 12:51:47 PM PDT 24 2519501072 ps
T399 /workspace/coverage/default/40.sram_ctrl_stress_all.4235607255 Mar 14 12:53:36 PM PDT 24 Mar 14 02:22:14 PM PDT 24 194865902115 ps
T400 /workspace/coverage/default/26.sram_ctrl_ram_cfg.1328888457 Mar 14 12:51:50 PM PDT 24 Mar 14 12:51:54 PM PDT 24 347211685 ps
T401 /workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3949016647 Mar 14 12:51:20 PM PDT 24 Mar 14 12:51:43 PM PDT 24 627576846 ps
T402 /workspace/coverage/default/23.sram_ctrl_mem_partial_access.2282435060 Mar 14 12:51:34 PM PDT 24 Mar 14 12:53:56 PM PDT 24 9292625193 ps
T403 /workspace/coverage/default/6.sram_ctrl_access_during_key_req.2479322441 Mar 14 12:50:46 PM PDT 24 Mar 14 12:59:50 PM PDT 24 4513893158 ps
T404 /workspace/coverage/default/42.sram_ctrl_stress_pipeline.255647250 Mar 14 12:53:46 PM PDT 24 Mar 14 12:57:07 PM PDT 24 13409072959 ps
T405 /workspace/coverage/default/42.sram_ctrl_access_during_key_req.2139674493 Mar 14 12:53:54 PM PDT 24 Mar 14 12:59:01 PM PDT 24 30222795317 ps
T406 /workspace/coverage/default/43.sram_ctrl_partial_access.572697894 Mar 14 12:53:53 PM PDT 24 Mar 14 12:54:09 PM PDT 24 10391283432 ps
T407 /workspace/coverage/default/47.sram_ctrl_bijection.3816403837 Mar 14 12:54:37 PM PDT 24 Mar 14 01:23:00 PM PDT 24 48845255286 ps
T408 /workspace/coverage/default/49.sram_ctrl_lc_escalation.3509987888 Mar 14 12:55:02 PM PDT 24 Mar 14 12:56:26 PM PDT 24 13068895753 ps
T409 /workspace/coverage/default/49.sram_ctrl_stress_all.3826384674 Mar 14 12:54:59 PM PDT 24 Mar 14 01:37:25 PM PDT 24 653257995629 ps
T410 /workspace/coverage/default/42.sram_ctrl_partial_access.1208022994 Mar 14 12:53:44 PM PDT 24 Mar 14 12:54:09 PM PDT 24 3069102858 ps
T411 /workspace/coverage/default/41.sram_ctrl_max_throughput.590579389 Mar 14 12:53:42 PM PDT 24 Mar 14 12:56:29 PM PDT 24 1600231949 ps
T412 /workspace/coverage/default/37.sram_ctrl_lc_escalation.2979443364 Mar 14 12:53:04 PM PDT 24 Mar 14 12:54:29 PM PDT 24 65901585355 ps
T413 /workspace/coverage/default/24.sram_ctrl_stress_all_with_rand_reset.3807208049 Mar 14 12:51:41 PM PDT 24 Mar 14 12:51:46 PM PDT 24 95754950 ps
T414 /workspace/coverage/default/8.sram_ctrl_executable.355629489 Mar 14 12:50:59 PM PDT 24 Mar 14 12:59:31 PM PDT 24 12877110706 ps
T415 /workspace/coverage/default/10.sram_ctrl_smoke.1492899707 Mar 14 12:50:52 PM PDT 24 Mar 14 12:52:44 PM PDT 24 5938658874 ps
T416 /workspace/coverage/default/30.sram_ctrl_lc_escalation.804342945 Mar 14 12:52:16 PM PDT 24 Mar 14 12:53:19 PM PDT 24 44215147807 ps
T417 /workspace/coverage/default/43.sram_ctrl_max_throughput.3991372604 Mar 14 12:53:52 PM PDT 24 Mar 14 12:54:16 PM PDT 24 2610189588 ps
T111 /workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.602560273 Mar 14 12:50:36 PM PDT 24 Mar 14 12:50:52 PM PDT 24 483458053 ps
T418 /workspace/coverage/default/49.sram_ctrl_executable.3494339068 Mar 14 12:54:58 PM PDT 24 Mar 14 01:00:21 PM PDT 24 5168804055 ps
T419 /workspace/coverage/default/13.sram_ctrl_bijection.3610004911 Mar 14 12:51:11 PM PDT 24 Mar 14 01:18:22 PM PDT 24 153566454672 ps
T420 /workspace/coverage/default/48.sram_ctrl_stress_all_with_rand_reset.3346503141 Mar 14 12:54:51 PM PDT 24 Mar 14 12:55:14 PM PDT 24 2487479073 ps
T421 /workspace/coverage/default/47.sram_ctrl_executable.1527225668 Mar 14 12:54:48 PM PDT 24 Mar 14 12:58:02 PM PDT 24 7649920672 ps
T422 /workspace/coverage/default/7.sram_ctrl_smoke.1212367256 Mar 14 12:50:51 PM PDT 24 Mar 14 12:50:56 PM PDT 24 1362170725 ps
T423 /workspace/coverage/default/23.sram_ctrl_bijection.324375418 Mar 14 12:51:28 PM PDT 24 Mar 14 01:35:35 PM PDT 24 146418170431 ps
T424 /workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3121446679 Mar 14 12:50:33 PM PDT 24 Mar 14 12:53:48 PM PDT 24 1473431179 ps
T425 /workspace/coverage/default/15.sram_ctrl_mem_walk.2285285601 Mar 14 12:51:07 PM PDT 24 Mar 14 12:55:15 PM PDT 24 10107932641 ps
T426 /workspace/coverage/default/46.sram_ctrl_throughput_w_partial_write.971915094 Mar 14 12:54:27 PM PDT 24 Mar 14 12:55:18 PM PDT 24 744022467 ps
T427 /workspace/coverage/default/12.sram_ctrl_partial_access.2734860931 Mar 14 12:51:10 PM PDT 24 Mar 14 12:53:38 PM PDT 24 879120563 ps
T428 /workspace/coverage/default/16.sram_ctrl_multiple_keys.3652561435 Mar 14 12:51:18 PM PDT 24 Mar 14 01:08:30 PM PDT 24 34282728897 ps
T429 /workspace/coverage/default/26.sram_ctrl_bijection.1108699323 Mar 14 12:51:49 PM PDT 24 Mar 14 12:59:19 PM PDT 24 49218035670 ps
T430 /workspace/coverage/default/26.sram_ctrl_stress_all.4150219262 Mar 14 12:51:49 PM PDT 24 Mar 14 01:52:09 PM PDT 24 647250099489 ps
T431 /workspace/coverage/default/42.sram_ctrl_ram_cfg.2780288769 Mar 14 12:53:55 PM PDT 24 Mar 14 12:53:58 PM PDT 24 364128715 ps
T432 /workspace/coverage/default/8.sram_ctrl_alert_test.2492793479 Mar 14 12:50:58 PM PDT 24 Mar 14 12:50:59 PM PDT 24 38386669 ps
T433 /workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.4114673599 Mar 14 12:53:54 PM PDT 24 Mar 14 12:54:53 PM PDT 24 5405676628 ps
T434 /workspace/coverage/default/17.sram_ctrl_stress_all.2930150611 Mar 14 12:51:17 PM PDT 24 Mar 14 02:07:20 PM PDT 24 190993729122 ps
T435 /workspace/coverage/default/12.sram_ctrl_partial_access_b2b.3400126622 Mar 14 12:51:08 PM PDT 24 Mar 14 12:58:27 PM PDT 24 69115090802 ps
T436 /workspace/coverage/default/28.sram_ctrl_lc_escalation.63247914 Mar 14 12:52:05 PM PDT 24 Mar 14 12:52:37 PM PDT 24 16014808450 ps
T437 /workspace/coverage/default/45.sram_ctrl_smoke.3582842041 Mar 14 12:54:03 PM PDT 24 Mar 14 12:54:18 PM PDT 24 1035195103 ps
T438 /workspace/coverage/default/16.sram_ctrl_partial_access_b2b.2928484071 Mar 14 12:51:10 PM PDT 24 Mar 14 12:56:08 PM PDT 24 14147800785 ps
T439 /workspace/coverage/default/16.sram_ctrl_max_throughput.1907457390 Mar 14 12:51:08 PM PDT 24 Mar 14 12:51:39 PM PDT 24 3574787416 ps
T440 /workspace/coverage/default/22.sram_ctrl_mem_partial_access.1579327086 Mar 14 12:51:28 PM PDT 24 Mar 14 12:52:46 PM PDT 24 2454571806 ps
T441 /workspace/coverage/default/23.sram_ctrl_ram_cfg.2952811926 Mar 14 12:51:30 PM PDT 24 Mar 14 12:51:35 PM PDT 24 3067394428 ps
T442 /workspace/coverage/default/26.sram_ctrl_multiple_keys.3380895316 Mar 14 12:51:48 PM PDT 24 Mar 14 01:06:41 PM PDT 24 18376913381 ps
T443 /workspace/coverage/default/41.sram_ctrl_mem_walk.3353342547 Mar 14 12:53:43 PM PDT 24 Mar 14 12:55:48 PM PDT 24 7896052337 ps
T444 /workspace/coverage/default/47.sram_ctrl_stress_pipeline.1463050809 Mar 14 12:54:37 PM PDT 24 Mar 14 12:59:30 PM PDT 24 8127255899 ps
T445 /workspace/coverage/default/34.sram_ctrl_partial_access_b2b.3210220519 Mar 14 12:52:48 PM PDT 24 Mar 14 12:59:20 PM PDT 24 38948322524 ps
T446 /workspace/coverage/default/11.sram_ctrl_bijection.3772541596 Mar 14 12:51:04 PM PDT 24 Mar 14 01:18:43 PM PDT 24 88633474216 ps
T447 /workspace/coverage/default/44.sram_ctrl_stress_all.2660107609 Mar 14 12:54:01 PM PDT 24 Mar 14 01:59:57 PM PDT 24 47298558620 ps
T448 /workspace/coverage/default/5.sram_ctrl_executable.606510102 Mar 14 12:50:47 PM PDT 24 Mar 14 01:17:14 PM PDT 24 21103996693 ps
T449 /workspace/coverage/default/13.sram_ctrl_stress_all.2364745974 Mar 14 12:51:05 PM PDT 24 Mar 14 02:25:26 PM PDT 24 373732206509 ps
T450 /workspace/coverage/default/8.sram_ctrl_mem_partial_access.2282989511 Mar 14 12:50:54 PM PDT 24 Mar 14 12:52:01 PM PDT 24 1313145483 ps
T451 /workspace/coverage/default/41.sram_ctrl_regwen.84243162 Mar 14 12:53:42 PM PDT 24 Mar 14 01:15:04 PM PDT 24 73088523581 ps
T452 /workspace/coverage/default/4.sram_ctrl_lc_escalation.1888674128 Mar 14 12:50:34 PM PDT 24 Mar 14 12:51:05 PM PDT 24 5419355266 ps
T112 /workspace/coverage/default/30.sram_ctrl_stress_all_with_rand_reset.3421861160 Mar 14 12:52:15 PM PDT 24 Mar 14 12:53:08 PM PDT 24 4381882892 ps
T453 /workspace/coverage/default/28.sram_ctrl_bijection.3338534922 Mar 14 12:51:56 PM PDT 24 Mar 14 01:04:07 PM PDT 24 10855387418 ps
T454 /workspace/coverage/default/39.sram_ctrl_regwen.3090286999 Mar 14 12:53:24 PM PDT 24 Mar 14 01:04:10 PM PDT 24 12761938563 ps
T455 /workspace/coverage/default/47.sram_ctrl_regwen.1020509312 Mar 14 12:54:51 PM PDT 24 Mar 14 01:17:12 PM PDT 24 45583343245 ps
T456 /workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.1974879453 Mar 14 12:52:13 PM PDT 24 Mar 14 12:52:28 PM PDT 24 2775465063 ps
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T460 /workspace/coverage/default/25.sram_ctrl_bijection.1683274472 Mar 14 12:51:39 PM PDT 24 Mar 14 01:06:30 PM PDT 24 115386813654 ps
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T515 /workspace/coverage/default/19.sram_ctrl_max_throughput.245410366 Mar 14 12:51:16 PM PDT 24 Mar 14 12:52:36 PM PDT 24 770751705 ps
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T526 /workspace/coverage/default/21.sram_ctrl_partial_access.834654836 Mar 14 12:51:09 PM PDT 24 Mar 14 12:51:29 PM PDT 24 1818679255 ps
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T530 /workspace/coverage/default/2.sram_ctrl_lc_escalation.813914607 Mar 14 12:50:37 PM PDT 24 Mar 14 12:52:25 PM PDT 24 65639274100 ps
T531 /workspace/coverage/default/31.sram_ctrl_executable.156053995 Mar 14 12:52:27 PM PDT 24 Mar 14 12:56:06 PM PDT 24 11262903438 ps
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T538 /workspace/coverage/default/11.sram_ctrl_mem_partial_access.1234074671 Mar 14 12:51:09 PM PDT 24 Mar 14 12:53:30 PM PDT 24 4528494229 ps
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T548 /workspace/coverage/default/27.sram_ctrl_throughput_w_partial_write.2261217011 Mar 14 12:51:54 PM PDT 24 Mar 14 12:53:26 PM PDT 24 1634897693 ps
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T550 /workspace/coverage/default/25.sram_ctrl_regwen.2279787815 Mar 14 12:51:49 PM PDT 24 Mar 14 01:04:40 PM PDT 24 17851404050 ps
T551 /workspace/coverage/default/39.sram_ctrl_max_throughput.928466147 Mar 14 12:53:24 PM PDT 24 Mar 14 12:55:37 PM PDT 24 767267480 ps
T552 /workspace/coverage/default/6.sram_ctrl_lc_escalation.2235966843 Mar 14 12:50:41 PM PDT 24 Mar 14 12:51:51 PM PDT 24 12343478728 ps
T553 /workspace/coverage/default/35.sram_ctrl_mem_partial_access.2528093880 Mar 14 12:52:48 PM PDT 24 Mar 14 12:55:05 PM PDT 24 4761804098 ps
T554 /workspace/coverage/default/39.sram_ctrl_multiple_keys.1550476064 Mar 14 12:53:24 PM PDT 24 Mar 14 01:09:05 PM PDT 24 47510995218 ps
T555 /workspace/coverage/default/39.sram_ctrl_bijection.3921225518 Mar 14 12:53:24 PM PDT 24 Mar 14 01:27:58 PM PDT 24 59611169251 ps
T556 /workspace/coverage/default/5.sram_ctrl_mem_partial_access.2129709703 Mar 14 12:50:51 PM PDT 24 Mar 14 12:51:55 PM PDT 24 3806728949 ps
T557 /workspace/coverage/default/13.sram_ctrl_smoke.1960386904 Mar 14 12:51:08 PM PDT 24 Mar 14 12:51:15 PM PDT 24 2854686087 ps
T558 /workspace/coverage/default/49.sram_ctrl_bijection.2151006894 Mar 14 12:54:59 PM PDT 24 Mar 14 01:24:17 PM PDT 24 30812176289 ps
T559 /workspace/coverage/default/28.sram_ctrl_regwen.581384483 Mar 14 12:52:03 PM PDT 24 Mar 14 01:09:44 PM PDT 24 77677099666 ps
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