| T794 |
/workspace/coverage/default/5.sram_ctrl_smoke.3346826535 |
|
|
Mar 14 12:50:51 PM PDT 24 |
Mar 14 12:51:03 PM PDT 24 |
776151456 ps |
| T795 |
/workspace/coverage/default/2.sram_ctrl_mem_walk.3528911464 |
|
|
Mar 14 12:50:32 PM PDT 24 |
Mar 14 12:53:05 PM PDT 24 |
36297085239 ps |
| T116 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.2980987222 |
|
|
Mar 14 12:50:53 PM PDT 24 |
Mar 14 12:51:02 PM PDT 24 |
315391573 ps |
| T796 |
/workspace/coverage/default/5.sram_ctrl_bijection.3779936623 |
|
|
Mar 14 12:50:52 PM PDT 24 |
Mar 14 01:05:39 PM PDT 24 |
50105952671 ps |
| T797 |
/workspace/coverage/default/5.sram_ctrl_multiple_keys.1190297458 |
|
|
Mar 14 12:50:53 PM PDT 24 |
Mar 14 12:56:17 PM PDT 24 |
12775628963 ps |
| T798 |
/workspace/coverage/default/24.sram_ctrl_alert_test.4263865873 |
|
|
Mar 14 12:51:39 PM PDT 24 |
Mar 14 12:51:39 PM PDT 24 |
47324464 ps |
| T799 |
/workspace/coverage/default/15.sram_ctrl_stress_all.997474973 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 01:10:38 PM PDT 24 |
548916245514 ps |
| T800 |
/workspace/coverage/default/49.sram_ctrl_ram_cfg.3249883378 |
|
|
Mar 14 12:55:02 PM PDT 24 |
Mar 14 12:55:07 PM PDT 24 |
1358186778 ps |
| T801 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.2774191444 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:51:21 PM PDT 24 |
1346692480 ps |
| T802 |
/workspace/coverage/default/11.sram_ctrl_executable.3895021064 |
|
|
Mar 14 12:51:06 PM PDT 24 |
Mar 14 01:08:41 PM PDT 24 |
16527146832 ps |
| T803 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.83638680 |
|
|
Mar 14 12:52:53 PM PDT 24 |
Mar 14 12:59:37 PM PDT 24 |
35545765629 ps |
| T804 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.2765898104 |
|
|
Mar 14 12:50:38 PM PDT 24 |
Mar 14 12:54:48 PM PDT 24 |
15763756020 ps |
| T805 |
/workspace/coverage/default/15.sram_ctrl_multiple_keys.757061657 |
|
|
Mar 14 12:51:06 PM PDT 24 |
Mar 14 01:11:20 PM PDT 24 |
79051680613 ps |
| T806 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.4166534138 |
|
|
Mar 14 12:54:38 PM PDT 24 |
Mar 14 12:56:23 PM PDT 24 |
15625646791 ps |
| T807 |
/workspace/coverage/default/23.sram_ctrl_executable.1297842976 |
|
|
Mar 14 12:51:29 PM PDT 24 |
Mar 14 01:02:19 PM PDT 24 |
27067085586 ps |
| T808 |
/workspace/coverage/default/31.sram_ctrl_alert_test.1484009260 |
|
|
Mar 14 12:52:26 PM PDT 24 |
Mar 14 12:52:27 PM PDT 24 |
64572158 ps |
| T809 |
/workspace/coverage/default/44.sram_ctrl_partial_access.3670990770 |
|
|
Mar 14 12:54:04 PM PDT 24 |
Mar 14 12:54:13 PM PDT 24 |
1555475273 ps |
| T810 |
/workspace/coverage/default/16.sram_ctrl_partial_access.2812013205 |
|
|
Mar 14 12:51:04 PM PDT 24 |
Mar 14 12:51:22 PM PDT 24 |
1625892949 ps |
| T811 |
/workspace/coverage/default/19.sram_ctrl_smoke.1509408438 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 12:51:27 PM PDT 24 |
8724372240 ps |
| T812 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2889782045 |
|
|
Mar 14 12:51:22 PM PDT 24 |
Mar 14 12:51:30 PM PDT 24 |
2818444602 ps |
| T813 |
/workspace/coverage/default/47.sram_ctrl_alert_test.2563986794 |
|
|
Mar 14 12:54:49 PM PDT 24 |
Mar 14 12:54:50 PM PDT 24 |
12763642 ps |
| T814 |
/workspace/coverage/default/10.sram_ctrl_stress_pipeline.57523339 |
|
|
Mar 14 12:51:06 PM PDT 24 |
Mar 14 12:54:26 PM PDT 24 |
6854935141 ps |
| T815 |
/workspace/coverage/default/12.sram_ctrl_throughput_w_partial_write.1149588445 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:51:46 PM PDT 24 |
3053387411 ps |
| T816 |
/workspace/coverage/default/31.sram_ctrl_multiple_keys.3408326521 |
|
|
Mar 14 12:52:31 PM PDT 24 |
Mar 14 01:13:54 PM PDT 24 |
73377512708 ps |
| T817 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.2987151428 |
|
|
Mar 14 12:54:13 PM PDT 24 |
Mar 14 12:59:56 PM PDT 24 |
40129622509 ps |
| T818 |
/workspace/coverage/default/12.sram_ctrl_bijection.3368066880 |
|
|
Mar 14 12:51:08 PM PDT 24 |
Mar 14 01:10:02 PM PDT 24 |
66945685734 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_max_throughput.4247204385 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 12:53:58 PM PDT 24 |
764233980 ps |
| T820 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1623745119 |
|
|
Mar 14 12:51:49 PM PDT 24 |
Mar 14 12:51:50 PM PDT 24 |
16075918 ps |
| T821 |
/workspace/coverage/default/9.sram_ctrl_stress_all.3337827296 |
|
|
Mar 14 12:50:56 PM PDT 24 |
Mar 14 01:47:49 PM PDT 24 |
217874647998 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_mem_partial_access.1666731612 |
|
|
Mar 14 12:51:39 PM PDT 24 |
Mar 14 12:54:21 PM PDT 24 |
30082271502 ps |
| T823 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.458905455 |
|
|
Mar 14 12:54:47 PM PDT 24 |
Mar 14 12:54:51 PM PDT 24 |
618561309 ps |
| T824 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.3868882837 |
|
|
Mar 14 12:53:35 PM PDT 24 |
Mar 14 12:54:40 PM PDT 24 |
33662789722 ps |
| T825 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.3404651571 |
|
|
Mar 14 12:51:19 PM PDT 24 |
Mar 14 12:52:26 PM PDT 24 |
774213240 ps |
| T826 |
/workspace/coverage/default/9.sram_ctrl_partial_access.549366361 |
|
|
Mar 14 12:50:49 PM PDT 24 |
Mar 14 12:52:09 PM PDT 24 |
4431922920 ps |
| T827 |
/workspace/coverage/default/19.sram_ctrl_stress_all.525540107 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 01:12:36 PM PDT 24 |
49795140002 ps |
| T828 |
/workspace/coverage/default/48.sram_ctrl_access_during_key_req.3156110044 |
|
|
Mar 14 12:54:47 PM PDT 24 |
Mar 14 01:13:02 PM PDT 24 |
28654074696 ps |
| T829 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.4114405216 |
|
|
Mar 14 12:53:55 PM PDT 24 |
Mar 14 12:56:02 PM PDT 24 |
7897974009 ps |
| T830 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.640022870 |
|
|
Mar 14 12:52:28 PM PDT 24 |
Mar 14 12:58:17 PM PDT 24 |
14379298719 ps |
| T831 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.979019925 |
|
|
Mar 14 12:52:50 PM PDT 24 |
Mar 14 12:52:55 PM PDT 24 |
162260103 ps |
| T832 |
/workspace/coverage/default/19.sram_ctrl_partial_access.4064599847 |
|
|
Mar 14 12:51:14 PM PDT 24 |
Mar 14 12:51:22 PM PDT 24 |
1586396937 ps |
| T833 |
/workspace/coverage/default/11.sram_ctrl_alert_test.1969225009 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:51:06 PM PDT 24 |
36980167 ps |
| T834 |
/workspace/coverage/default/2.sram_ctrl_alert_test.1816657259 |
|
|
Mar 14 12:50:35 PM PDT 24 |
Mar 14 12:50:36 PM PDT 24 |
20700339 ps |
| T835 |
/workspace/coverage/default/49.sram_ctrl_regwen.814461360 |
|
|
Mar 14 12:55:00 PM PDT 24 |
Mar 14 01:03:37 PM PDT 24 |
68071161593 ps |
| T836 |
/workspace/coverage/default/17.sram_ctrl_partial_access_b2b.790545773 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 12:54:29 PM PDT 24 |
15814079679 ps |
| T837 |
/workspace/coverage/default/7.sram_ctrl_bijection.2622498127 |
|
|
Mar 14 12:50:51 PM PDT 24 |
Mar 14 01:13:29 PM PDT 24 |
41664548401 ps |
| T838 |
/workspace/coverage/default/46.sram_ctrl_stress_pipeline.3654520649 |
|
|
Mar 14 12:54:27 PM PDT 24 |
Mar 14 01:01:36 PM PDT 24 |
100981098439 ps |
| T839 |
/workspace/coverage/default/43.sram_ctrl_ram_cfg.460206766 |
|
|
Mar 14 12:54:01 PM PDT 24 |
Mar 14 12:54:04 PM PDT 24 |
1356282508 ps |
| T840 |
/workspace/coverage/default/2.sram_ctrl_smoke.491850391 |
|
|
Mar 14 12:50:27 PM PDT 24 |
Mar 14 12:50:34 PM PDT 24 |
457110611 ps |
| T841 |
/workspace/coverage/default/30.sram_ctrl_ram_cfg.3412812941 |
|
|
Mar 14 12:52:14 PM PDT 24 |
Mar 14 12:52:18 PM PDT 24 |
1462495830 ps |
| T842 |
/workspace/coverage/default/37.sram_ctrl_partial_access.4177178834 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 12:53:10 PM PDT 24 |
746873496 ps |
| T843 |
/workspace/coverage/default/36.sram_ctrl_stress_all_with_rand_reset.1341687427 |
|
|
Mar 14 12:53:04 PM PDT 24 |
Mar 14 12:53:11 PM PDT 24 |
249979539 ps |
| T844 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.1101764219 |
|
|
Mar 14 12:54:13 PM PDT 24 |
Mar 14 12:55:14 PM PDT 24 |
152853409649 ps |
| T845 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2409889617 |
|
|
Mar 14 12:51:19 PM PDT 24 |
Mar 14 12:52:15 PM PDT 24 |
4839446510 ps |
| T846 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1562697269 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 12:51:19 PM PDT 24 |
42081996 ps |
| T847 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.660887304 |
|
|
Mar 14 12:53:35 PM PDT 24 |
Mar 14 01:00:40 PM PDT 24 |
8524991769 ps |
| T848 |
/workspace/coverage/default/19.sram_ctrl_mem_walk.1008718576 |
|
|
Mar 14 12:51:15 PM PDT 24 |
Mar 14 12:54:16 PM PDT 24 |
206261472742 ps |
| T849 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2418090750 |
|
|
Mar 14 12:52:27 PM PDT 24 |
Mar 14 12:53:11 PM PDT 24 |
4425003477 ps |
| T850 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.1669018843 |
|
|
Mar 14 12:53:19 PM PDT 24 |
Mar 14 01:01:14 PM PDT 24 |
32701242025 ps |
| T851 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.119339972 |
|
|
Mar 14 12:52:03 PM PDT 24 |
Mar 14 12:52:32 PM PDT 24 |
7101655827 ps |
| T852 |
/workspace/coverage/default/38.sram_ctrl_bijection.580920067 |
|
|
Mar 14 12:53:14 PM PDT 24 |
Mar 14 01:35:30 PM PDT 24 |
111582642004 ps |
| T853 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.3352000903 |
|
|
Mar 14 12:51:22 PM PDT 24 |
Mar 14 12:52:44 PM PDT 24 |
16330029710 ps |
| T854 |
/workspace/coverage/default/20.sram_ctrl_access_during_key_req.3288471053 |
|
|
Mar 14 12:51:16 PM PDT 24 |
Mar 14 01:02:33 PM PDT 24 |
8010460450 ps |
| T855 |
/workspace/coverage/default/35.sram_ctrl_smoke.356847612 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:53:00 PM PDT 24 |
1721798330 ps |
| T856 |
/workspace/coverage/default/5.sram_ctrl_ram_cfg.2906211982 |
|
|
Mar 14 12:50:47 PM PDT 24 |
Mar 14 12:50:50 PM PDT 24 |
361102143 ps |
| T857 |
/workspace/coverage/default/13.sram_ctrl_regwen.2813601739 |
|
|
Mar 14 12:51:12 PM PDT 24 |
Mar 14 01:09:44 PM PDT 24 |
91945299644 ps |
| T858 |
/workspace/coverage/default/26.sram_ctrl_partial_access_b2b.3854422509 |
|
|
Mar 14 12:51:53 PM PDT 24 |
Mar 14 12:58:59 PM PDT 24 |
126404493366 ps |
| T859 |
/workspace/coverage/default/13.sram_ctrl_throughput_w_partial_write.1919316486 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:51:52 PM PDT 24 |
4111807404 ps |
| T860 |
/workspace/coverage/default/6.sram_ctrl_regwen.4223378744 |
|
|
Mar 14 12:50:35 PM PDT 24 |
Mar 14 01:14:00 PM PDT 24 |
22407752435 ps |
| T861 |
/workspace/coverage/default/16.sram_ctrl_regwen.2846453866 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 01:00:40 PM PDT 24 |
27689002355 ps |
| T862 |
/workspace/coverage/default/15.sram_ctrl_smoke.3767264008 |
|
|
Mar 14 12:51:10 PM PDT 24 |
Mar 14 12:53:13 PM PDT 24 |
1305623634 ps |
| T863 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3593712596 |
|
|
Mar 14 12:51:25 PM PDT 24 |
Mar 14 01:26:37 PM PDT 24 |
54020720944 ps |
| T864 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.1953970343 |
|
|
Mar 14 12:54:24 PM PDT 24 |
Mar 14 12:56:13 PM PDT 24 |
785703745 ps |
| T865 |
/workspace/coverage/default/46.sram_ctrl_alert_test.4290488942 |
|
|
Mar 14 12:54:37 PM PDT 24 |
Mar 14 12:54:38 PM PDT 24 |
15668969 ps |
| T866 |
/workspace/coverage/default/0.sram_ctrl_bijection.4141676899 |
|
|
Mar 14 12:50:41 PM PDT 24 |
Mar 14 01:01:52 PM PDT 24 |
115896305330 ps |
| T867 |
/workspace/coverage/default/15.sram_ctrl_bijection.2474745653 |
|
|
Mar 14 12:51:04 PM PDT 24 |
Mar 14 01:25:04 PM PDT 24 |
211690273100 ps |
| T868 |
/workspace/coverage/default/2.sram_ctrl_max_throughput.3316754771 |
|
|
Mar 14 12:50:36 PM PDT 24 |
Mar 14 12:50:44 PM PDT 24 |
682830137 ps |
| T869 |
/workspace/coverage/default/48.sram_ctrl_mem_walk.683019269 |
|
|
Mar 14 12:54:48 PM PDT 24 |
Mar 14 12:57:31 PM PDT 24 |
10766923822 ps |
| T870 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1787179756 |
|
|
Mar 14 12:50:52 PM PDT 24 |
Mar 14 02:31:25 PM PDT 24 |
425738876726 ps |
| T871 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.3048400218 |
|
|
Mar 14 12:51:09 PM PDT 24 |
Mar 14 12:51:36 PM PDT 24 |
718316858 ps |
| T872 |
/workspace/coverage/default/30.sram_ctrl_smoke.445883689 |
|
|
Mar 14 12:52:16 PM PDT 24 |
Mar 14 12:52:31 PM PDT 24 |
1980446093 ps |
| T873 |
/workspace/coverage/default/31.sram_ctrl_stress_all.1686720200 |
|
|
Mar 14 12:52:28 PM PDT 24 |
Mar 14 01:40:31 PM PDT 24 |
106038007574 ps |
| T874 |
/workspace/coverage/default/41.sram_ctrl_ram_cfg.2042081884 |
|
|
Mar 14 12:53:45 PM PDT 24 |
Mar 14 12:53:49 PM PDT 24 |
362269474 ps |
| T875 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.3314964069 |
|
|
Mar 14 12:53:03 PM PDT 24 |
Mar 14 12:59:00 PM PDT 24 |
23781989727 ps |
| T876 |
/workspace/coverage/default/33.sram_ctrl_alert_test.1626741980 |
|
|
Mar 14 12:52:47 PM PDT 24 |
Mar 14 12:52:47 PM PDT 24 |
22355947 ps |
| T877 |
/workspace/coverage/default/33.sram_ctrl_max_throughput.3256985037 |
|
|
Mar 14 12:52:38 PM PDT 24 |
Mar 14 12:54:50 PM PDT 24 |
1550304891 ps |
| T878 |
/workspace/coverage/default/34.sram_ctrl_partial_access.2313591159 |
|
|
Mar 14 12:52:46 PM PDT 24 |
Mar 14 12:53:05 PM PDT 24 |
6563827529 ps |
| T879 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.1844887531 |
|
|
Mar 14 12:52:04 PM PDT 24 |
Mar 14 12:57:22 PM PDT 24 |
19368833509 ps |
| T880 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.490421099 |
|
|
Mar 14 12:51:00 PM PDT 24 |
Mar 14 01:05:51 PM PDT 24 |
13201898712 ps |
| T881 |
/workspace/coverage/default/43.sram_ctrl_mem_walk.1224607211 |
|
|
Mar 14 12:54:02 PM PDT 24 |
Mar 14 12:59:25 PM PDT 24 |
89394459563 ps |
| T882 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.1099672280 |
|
|
Mar 14 12:51:56 PM PDT 24 |
Mar 14 12:52:39 PM PDT 24 |
6116003167 ps |
| T883 |
/workspace/coverage/default/37.sram_ctrl_alert_test.90746957 |
|
|
Mar 14 12:53:19 PM PDT 24 |
Mar 14 12:53:20 PM PDT 24 |
32617139 ps |
| T884 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.1016866409 |
|
|
Mar 14 12:51:16 PM PDT 24 |
Mar 14 12:55:32 PM PDT 24 |
16417929149 ps |
| T885 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1205577434 |
|
|
Mar 14 12:53:17 PM PDT 24 |
Mar 14 12:54:36 PM PDT 24 |
21267353092 ps |
| T886 |
/workspace/coverage/default/49.sram_ctrl_smoke.3754249840 |
|
|
Mar 14 12:54:59 PM PDT 24 |
Mar 14 12:55:06 PM PDT 24 |
2429274260 ps |
| T887 |
/workspace/coverage/default/26.sram_ctrl_partial_access.1047102555 |
|
|
Mar 14 12:51:48 PM PDT 24 |
Mar 14 12:52:23 PM PDT 24 |
1810646522 ps |
| T888 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.3356203609 |
|
|
Mar 14 12:50:42 PM PDT 24 |
Mar 14 12:50:52 PM PDT 24 |
438571533 ps |
| T889 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.791824207 |
|
|
Mar 14 12:52:48 PM PDT 24 |
Mar 14 12:58:19 PM PDT 24 |
18186782148 ps |
| T890 |
/workspace/coverage/default/29.sram_ctrl_stress_all.437208127 |
|
|
Mar 14 12:52:15 PM PDT 24 |
Mar 14 02:44:53 PM PDT 24 |
907271943367 ps |
| T891 |
/workspace/coverage/default/4.sram_ctrl_multiple_keys.32743440 |
|
|
Mar 14 12:50:45 PM PDT 24 |
Mar 14 12:56:52 PM PDT 24 |
3543314673 ps |
| T892 |
/workspace/coverage/default/20.sram_ctrl_max_throughput.1830417531 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:51:27 PM PDT 24 |
692396762 ps |
| T893 |
/workspace/coverage/default/27.sram_ctrl_lc_escalation.3827611157 |
|
|
Mar 14 12:51:55 PM PDT 24 |
Mar 14 12:53:20 PM PDT 24 |
13558849424 ps |
| T894 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.3303618248 |
|
|
Mar 14 12:51:08 PM PDT 24 |
Mar 14 12:59:55 PM PDT 24 |
86743660024 ps |
| T895 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.2887719390 |
|
|
Mar 14 12:51:06 PM PDT 24 |
Mar 14 12:59:38 PM PDT 24 |
22355789648 ps |
| T896 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1376753444 |
|
|
Mar 14 12:51:46 PM PDT 24 |
Mar 14 12:56:51 PM PDT 24 |
61694910957 ps |
| T897 |
/workspace/coverage/default/10.sram_ctrl_mem_walk.1889596061 |
|
|
Mar 14 12:51:00 PM PDT 24 |
Mar 14 12:53:19 PM PDT 24 |
7180452300 ps |
| T898 |
/workspace/coverage/default/27.sram_ctrl_bijection.1568672526 |
|
|
Mar 14 12:51:45 PM PDT 24 |
Mar 14 01:21:08 PM PDT 24 |
280478869345 ps |
| T899 |
/workspace/coverage/default/4.sram_ctrl_bijection.1764735577 |
|
|
Mar 14 12:50:35 PM PDT 24 |
Mar 14 01:02:51 PM PDT 24 |
86716996383 ps |
| T900 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1865304921 |
|
|
Mar 14 12:50:52 PM PDT 24 |
Mar 14 12:55:43 PM PDT 24 |
12128052749 ps |
| T901 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3541188767 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:51:45 PM PDT 24 |
2988935547 ps |
| T902 |
/workspace/coverage/default/25.sram_ctrl_ram_cfg.2142427018 |
|
|
Mar 14 12:51:47 PM PDT 24 |
Mar 14 12:51:50 PM PDT 24 |
370598369 ps |
| T903 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.3261802224 |
|
|
Mar 14 12:53:43 PM PDT 24 |
Mar 14 12:57:05 PM PDT 24 |
11809845577 ps |
| T904 |
/workspace/coverage/default/46.sram_ctrl_regwen.716617527 |
|
|
Mar 14 12:54:24 PM PDT 24 |
Mar 14 01:06:51 PM PDT 24 |
7295325238 ps |
| T905 |
/workspace/coverage/default/10.sram_ctrl_stress_all.4018649251 |
|
|
Mar 14 12:50:54 PM PDT 24 |
Mar 14 02:00:27 PM PDT 24 |
88491355352 ps |
| T906 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.510350028 |
|
|
Mar 14 12:54:02 PM PDT 24 |
Mar 14 12:56:07 PM PDT 24 |
8223709890 ps |
| T907 |
/workspace/coverage/default/6.sram_ctrl_ram_cfg.2348529630 |
|
|
Mar 14 12:50:47 PM PDT 24 |
Mar 14 12:50:56 PM PDT 24 |
344638076 ps |
| T908 |
/workspace/coverage/default/9.sram_ctrl_regwen.3848570368 |
|
|
Mar 14 12:50:55 PM PDT 24 |
Mar 14 12:52:34 PM PDT 24 |
8741743011 ps |
| T909 |
/workspace/coverage/default/32.sram_ctrl_mem_walk.2909354442 |
|
|
Mar 14 12:52:37 PM PDT 24 |
Mar 14 12:54:30 PM PDT 24 |
9864978198 ps |
| T910 |
/workspace/coverage/default/39.sram_ctrl_partial_access.2930414381 |
|
|
Mar 14 12:53:23 PM PDT 24 |
Mar 14 12:53:39 PM PDT 24 |
3450054738 ps |
| T911 |
/workspace/coverage/default/11.sram_ctrl_stress_all_with_rand_reset.1484484792 |
|
|
Mar 14 12:51:07 PM PDT 24 |
Mar 14 12:51:55 PM PDT 24 |
1836822482 ps |
| T912 |
/workspace/coverage/default/14.sram_ctrl_lc_escalation.2482292093 |
|
|
Mar 14 12:51:11 PM PDT 24 |
Mar 14 12:51:40 PM PDT 24 |
21883331427 ps |
| T913 |
/workspace/coverage/default/33.sram_ctrl_multiple_keys.2470755322 |
|
|
Mar 14 12:52:40 PM PDT 24 |
Mar 14 01:01:20 PM PDT 24 |
10884550829 ps |
| T914 |
/workspace/coverage/default/9.sram_ctrl_executable.4083259370 |
|
|
Mar 14 12:51:06 PM PDT 24 |
Mar 14 01:01:27 PM PDT 24 |
31591344154 ps |
| T915 |
/workspace/coverage/default/8.sram_ctrl_throughput_w_partial_write.408465395 |
|
|
Mar 14 12:50:53 PM PDT 24 |
Mar 14 12:51:20 PM PDT 24 |
782597712 ps |
| T916 |
/workspace/coverage/default/28.sram_ctrl_multiple_keys.714131392 |
|
|
Mar 14 12:51:56 PM PDT 24 |
Mar 14 01:18:50 PM PDT 24 |
44841582045 ps |
| T917 |
/workspace/coverage/default/23.sram_ctrl_stress_all.945467623 |
|
|
Mar 14 12:51:38 PM PDT 24 |
Mar 14 01:15:11 PM PDT 24 |
32052899426 ps |
| T918 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.3723683392 |
|
|
Mar 14 12:52:45 PM PDT 24 |
Mar 14 12:52:48 PM PDT 24 |
1345506170 ps |
| T919 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.4174464751 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 12:52:09 PM PDT 24 |
29446386961 ps |
| T920 |
/workspace/coverage/default/47.sram_ctrl_smoke.1570470571 |
|
|
Mar 14 12:54:37 PM PDT 24 |
Mar 14 12:54:49 PM PDT 24 |
761638290 ps |
| T921 |
/workspace/coverage/default/1.sram_ctrl_multiple_keys.2421843297 |
|
|
Mar 14 12:50:31 PM PDT 24 |
Mar 14 01:10:05 PM PDT 24 |
78588738796 ps |
| T922 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.2850856378 |
|
|
Mar 14 12:51:33 PM PDT 24 |
Mar 14 01:11:54 PM PDT 24 |
27440930971 ps |
| T923 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.1608850143 |
|
|
Mar 14 12:51:23 PM PDT 24 |
Mar 14 12:54:21 PM PDT 24 |
2724469610 ps |
| T924 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.1078833382 |
|
|
Mar 14 12:50:47 PM PDT 24 |
Mar 14 01:09:59 PM PDT 24 |
13965063121 ps |
| T925 |
/workspace/coverage/default/9.sram_ctrl_max_throughput.2731009235 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 12:51:20 PM PDT 24 |
730473116 ps |
| T926 |
/workspace/coverage/default/15.sram_ctrl_partial_access.500910062 |
|
|
Mar 14 12:51:12 PM PDT 24 |
Mar 14 12:51:33 PM PDT 24 |
2783721316 ps |
| T927 |
/workspace/coverage/default/19.sram_ctrl_lc_escalation.851723632 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 12:52:29 PM PDT 24 |
45813196494 ps |
| T928 |
/workspace/coverage/default/6.sram_ctrl_executable.3138946269 |
|
|
Mar 14 12:50:51 PM PDT 24 |
Mar 14 12:56:38 PM PDT 24 |
2473979014 ps |
| T929 |
/workspace/coverage/default/23.sram_ctrl_partial_access.554462116 |
|
|
Mar 14 12:51:38 PM PDT 24 |
Mar 14 12:51:48 PM PDT 24 |
1454446512 ps |
| T930 |
/workspace/coverage/default/2.sram_ctrl_bijection.3705638537 |
|
|
Mar 14 12:50:32 PM PDT 24 |
Mar 14 01:11:13 PM PDT 24 |
19090370084 ps |
| T931 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.3368292853 |
|
|
Mar 14 12:53:24 PM PDT 24 |
Mar 14 12:54:14 PM PDT 24 |
2454588405 ps |
| T932 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.3647271048 |
|
|
Mar 14 12:50:38 PM PDT 24 |
Mar 14 12:52:32 PM PDT 24 |
805116843 ps |
| T933 |
/workspace/coverage/default/18.sram_ctrl_stress_all.74785612 |
|
|
Mar 14 12:51:18 PM PDT 24 |
Mar 14 01:03:56 PM PDT 24 |
53322750810 ps |
| T934 |
/workspace/coverage/default/6.sram_ctrl_smoke.2553823298 |
|
|
Mar 14 12:50:50 PM PDT 24 |
Mar 14 12:50:58 PM PDT 24 |
442683895 ps |
| T935 |
/workspace/coverage/default/28.sram_ctrl_mem_walk.2356081555 |
|
|
Mar 14 12:52:04 PM PDT 24 |
Mar 14 12:54:13 PM PDT 24 |
7902243995 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_access_during_key_req.2029028225 |
|
|
Mar 14 12:51:05 PM PDT 24 |
Mar 14 01:11:10 PM PDT 24 |
39145194241 ps |
| T937 |
/workspace/coverage/default/36.sram_ctrl_regwen.1205751617 |
|
|
Mar 14 12:52:56 PM PDT 24 |
Mar 14 01:18:15 PM PDT 24 |
29478624609 ps |
| T938 |
/workspace/coverage/default/43.sram_ctrl_bijection.2151850458 |
|
|
Mar 14 12:53:53 PM PDT 24 |
Mar 14 01:02:59 PM PDT 24 |
8371037113 ps |
| T939 |
/workspace/coverage/default/29.sram_ctrl_bijection.1079990777 |
|
|
Mar 14 12:52:06 PM PDT 24 |
Mar 14 01:15:07 PM PDT 24 |
311470295009 ps |
| T940 |
/workspace/coverage/default/40.sram_ctrl_smoke.640063587 |
|
|
Mar 14 12:53:23 PM PDT 24 |
Mar 14 12:53:38 PM PDT 24 |
495851816 ps |
| T941 |
/workspace/coverage/default/20.sram_ctrl_multiple_keys.3512828512 |
|
|
Mar 14 12:51:22 PM PDT 24 |
Mar 14 01:15:28 PM PDT 24 |
259835097859 ps |
| T942 |
/workspace/coverage/default/14.sram_ctrl_stress_all_with_rand_reset.2298723501 |
|
|
Mar 14 12:51:17 PM PDT 24 |
Mar 14 12:52:38 PM PDT 24 |
8206793094 ps |
| T943 |
/workspace/coverage/default/48.sram_ctrl_stress_pipeline.1519550580 |
|
|
Mar 14 12:54:47 PM PDT 24 |
Mar 14 01:00:16 PM PDT 24 |
5106017466 ps |
| T944 |
/workspace/coverage/default/7.sram_ctrl_stress_pipeline.696675557 |
|
|
Mar 14 12:50:52 PM PDT 24 |
Mar 14 12:53:00 PM PDT 24 |
8077384400 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.855009047 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:28:12 PM PDT 24 |
23932375 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.656680506 |
|
|
Mar 14 12:28:08 PM PDT 24 |
Mar 14 12:28:10 PM PDT 24 |
659259362 ps |
| T63 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.110959342 |
|
|
Mar 14 12:28:06 PM PDT 24 |
Mar 14 12:29:02 PM PDT 24 |
14112632131 ps |
| T106 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.4129475918 |
|
|
Mar 14 12:28:07 PM PDT 24 |
Mar 14 12:28:08 PM PDT 24 |
248968819 ps |
| T95 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.744634476 |
|
|
Mar 14 12:28:14 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
89800294 ps |
| T945 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1114894045 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:28:14 PM PDT 24 |
281225959 ps |
| T946 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.3837609347 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:19 PM PDT 24 |
358538859 ps |
| T64 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.2496181547 |
|
|
Mar 14 12:29:16 PM PDT 24 |
Mar 14 12:29:16 PM PDT 24 |
21053342 ps |
| T104 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3196139238 |
|
|
Mar 14 12:28:35 PM PDT 24 |
Mar 14 12:28:36 PM PDT 24 |
65104253 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.3185851349 |
|
|
Mar 14 12:27:55 PM PDT 24 |
Mar 14 12:27:58 PM PDT 24 |
64940995 ps |
| T948 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2087467031 |
|
|
Mar 14 12:28:18 PM PDT 24 |
Mar 14 12:28:21 PM PDT 24 |
48819040 ps |
| T65 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.2445735280 |
|
|
Mar 14 12:28:12 PM PDT 24 |
Mar 14 12:28:36 PM PDT 24 |
3699717021 ps |
| T949 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.52643610 |
|
|
Mar 14 12:28:22 PM PDT 24 |
Mar 14 12:28:25 PM PDT 24 |
353232774 ps |
| T950 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2314346964 |
|
|
Mar 14 12:28:12 PM PDT 24 |
Mar 14 12:28:14 PM PDT 24 |
95355067 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2166388470 |
|
|
Mar 14 12:28:08 PM PDT 24 |
Mar 14 12:28:11 PM PDT 24 |
189670033 ps |
| T96 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.2602898565 |
|
|
Mar 14 12:29:20 PM PDT 24 |
Mar 14 12:29:22 PM PDT 24 |
50007286 ps |
| T952 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.208358488 |
|
|
Mar 14 12:28:06 PM PDT 24 |
Mar 14 12:28:10 PM PDT 24 |
1442752117 ps |
| T66 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3041604926 |
|
|
Mar 14 12:28:13 PM PDT 24 |
Mar 14 12:28:14 PM PDT 24 |
318501672 ps |
| T953 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.3171534415 |
|
|
Mar 14 12:27:53 PM PDT 24 |
Mar 14 12:27:55 PM PDT 24 |
70019931 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.166892281 |
|
|
Mar 14 12:28:04 PM PDT 24 |
Mar 14 12:28:05 PM PDT 24 |
56924261 ps |
| T97 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3520896518 |
|
|
Mar 14 12:27:51 PM PDT 24 |
Mar 14 12:27:52 PM PDT 24 |
16648016 ps |
| T68 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2170177158 |
|
|
Mar 14 12:27:57 PM PDT 24 |
Mar 14 12:28:23 PM PDT 24 |
11917549034 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2607644401 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
12497905 ps |
| T70 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1250656464 |
|
|
Mar 14 12:29:17 PM PDT 24 |
Mar 14 12:29:18 PM PDT 24 |
20146380 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.3789003913 |
|
|
Mar 14 12:28:20 PM PDT 24 |
Mar 14 12:28:23 PM PDT 24 |
703612576 ps |
| T71 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3779800442 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
28807432 ps |
| T955 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.4041648682 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
127673444 ps |
| T74 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.1727463974 |
|
|
Mar 14 12:28:06 PM PDT 24 |
Mar 14 12:28:33 PM PDT 24 |
7103156574 ps |
| T956 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1850170226 |
|
|
Mar 14 12:28:12 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
39355666 ps |
| T957 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.4229705492 |
|
|
Mar 14 12:27:58 PM PDT 24 |
Mar 14 12:27:59 PM PDT 24 |
23978007 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3359933566 |
|
|
Mar 14 12:28:19 PM PDT 24 |
Mar 14 12:28:21 PM PDT 24 |
443248915 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.2299648431 |
|
|
Mar 14 12:28:50 PM PDT 24 |
Mar 14 12:29:21 PM PDT 24 |
16783289338 ps |
| T959 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.1994803425 |
|
|
Mar 14 12:27:56 PM PDT 24 |
Mar 14 12:27:59 PM PDT 24 |
349741927 ps |
| T960 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3599919082 |
|
|
Mar 14 12:28:38 PM PDT 24 |
Mar 14 12:28:41 PM PDT 24 |
689143405 ps |
| T120 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2857041072 |
|
|
Mar 14 12:28:24 PM PDT 24 |
Mar 14 12:28:26 PM PDT 24 |
671608167 ps |
| T961 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.219291362 |
|
|
Mar 14 12:28:21 PM PDT 24 |
Mar 14 12:28:23 PM PDT 24 |
837161499 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1627197220 |
|
|
Mar 14 12:28:19 PM PDT 24 |
Mar 14 12:28:20 PM PDT 24 |
31422543 ps |
| T963 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3701146530 |
|
|
Mar 14 12:27:56 PM PDT 24 |
Mar 14 12:28:01 PM PDT 24 |
2465507255 ps |
| T964 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.4081280252 |
|
|
Mar 14 12:28:07 PM PDT 24 |
Mar 14 12:29:01 PM PDT 24 |
28270007533 ps |
| T127 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.1525396642 |
|
|
Mar 14 12:28:08 PM PDT 24 |
Mar 14 12:28:10 PM PDT 24 |
133094090 ps |
| T125 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2804802328 |
|
|
Mar 14 12:28:38 PM PDT 24 |
Mar 14 12:28:39 PM PDT 24 |
317713348 ps |
| T122 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4211530207 |
|
|
Mar 14 12:28:30 PM PDT 24 |
Mar 14 12:28:32 PM PDT 24 |
142050590 ps |
| T75 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.551565895 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:29:10 PM PDT 24 |
32099648560 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.824304281 |
|
|
Mar 14 12:27:59 PM PDT 24 |
Mar 14 12:28:00 PM PDT 24 |
64643913 ps |
| T966 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.362894028 |
|
|
Mar 14 12:29:22 PM PDT 24 |
Mar 14 12:29:27 PM PDT 24 |
1536420251 ps |
| T967 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.3233419758 |
|
|
Mar 14 12:28:13 PM PDT 24 |
Mar 14 12:29:09 PM PDT 24 |
29330560286 ps |
| T968 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.299896063 |
|
|
Mar 14 12:28:18 PM PDT 24 |
Mar 14 12:28:22 PM PDT 24 |
346709260 ps |
| T76 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2493535874 |
|
|
Mar 14 12:27:56 PM PDT 24 |
Mar 14 12:27:57 PM PDT 24 |
13604796 ps |
| T77 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.84810915 |
|
|
Mar 14 12:28:02 PM PDT 24 |
Mar 14 12:28:30 PM PDT 24 |
10897163325 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3065347986 |
|
|
Mar 14 12:28:20 PM PDT 24 |
Mar 14 12:28:21 PM PDT 24 |
46025158 ps |
| T970 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1578372637 |
|
|
Mar 14 12:28:35 PM PDT 24 |
Mar 14 12:28:39 PM PDT 24 |
733310841 ps |
| T971 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2875425771 |
|
|
Mar 14 12:27:53 PM PDT 24 |
Mar 14 12:27:56 PM PDT 24 |
59827580 ps |
| T972 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.676009109 |
|
|
Mar 14 12:27:47 PM PDT 24 |
Mar 14 12:27:49 PM PDT 24 |
15030117 ps |
| T973 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3875309543 |
|
|
Mar 14 12:27:57 PM PDT 24 |
Mar 14 12:27:58 PM PDT 24 |
19545034 ps |
| T974 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3249657894 |
|
|
Mar 14 12:28:12 PM PDT 24 |
Mar 14 12:28:13 PM PDT 24 |
24203167 ps |
| T975 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.370210935 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
1452561462 ps |
| T976 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.610779493 |
|
|
Mar 14 12:28:06 PM PDT 24 |
Mar 14 12:28:07 PM PDT 24 |
81819850 ps |
| T977 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.3909481107 |
|
|
Mar 14 12:28:08 PM PDT 24 |
Mar 14 12:28:08 PM PDT 24 |
32727661 ps |
| T978 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2039667983 |
|
|
Mar 14 12:28:14 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
25689964 ps |
| T979 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.965415573 |
|
|
Mar 14 12:28:38 PM PDT 24 |
Mar 14 12:28:39 PM PDT 24 |
17664205 ps |
| T980 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.1110765602 |
|
|
Mar 14 12:27:55 PM PDT 24 |
Mar 14 12:27:58 PM PDT 24 |
679214444 ps |
| T78 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2442185014 |
|
|
Mar 14 12:28:20 PM PDT 24 |
Mar 14 12:28:45 PM PDT 24 |
3876313486 ps |
| T87 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3716435971 |
|
|
Mar 14 12:28:02 PM PDT 24 |
Mar 14 12:28:04 PM PDT 24 |
23761164 ps |
| T981 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.2696679816 |
|
|
Mar 14 12:28:03 PM PDT 24 |
Mar 14 12:28:04 PM PDT 24 |
38112448 ps |
| T982 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.44894564 |
|
|
Mar 14 12:28:16 PM PDT 24 |
Mar 14 12:28:17 PM PDT 24 |
34622711 ps |
| T983 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.2624002926 |
|
|
Mar 14 12:27:54 PM PDT 24 |
Mar 14 12:27:59 PM PDT 24 |
126321137 ps |
| T984 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.4244794486 |
|
|
Mar 14 12:28:23 PM PDT 24 |
Mar 14 12:28:24 PM PDT 24 |
48345359 ps |
| T985 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4293059669 |
|
|
Mar 14 12:28:22 PM PDT 24 |
Mar 14 12:28:50 PM PDT 24 |
14885481374 ps |
| T986 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.2597780773 |
|
|
Mar 14 12:28:19 PM PDT 24 |
Mar 14 12:28:20 PM PDT 24 |
27317156 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4165358351 |
|
|
Mar 14 12:28:21 PM PDT 24 |
Mar 14 12:28:27 PM PDT 24 |
40391865 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.2194154886 |
|
|
Mar 14 12:28:13 PM PDT 24 |
Mar 14 12:28:17 PM PDT 24 |
1467557666 ps |
| T126 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1874849119 |
|
|
Mar 14 12:28:14 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
375153718 ps |
| T123 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.3611697316 |
|
|
Mar 14 12:27:55 PM PDT 24 |
Mar 14 12:27:58 PM PDT 24 |
559150426 ps |
| T989 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.413567566 |
|
|
Mar 14 12:28:13 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
970164894 ps |
| T88 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3640090069 |
|
|
Mar 14 12:28:24 PM PDT 24 |
Mar 14 12:28:25 PM PDT 24 |
47205013 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.3127516278 |
|
|
Mar 14 12:28:23 PM PDT 24 |
Mar 14 12:29:12 PM PDT 24 |
9775566694 ps |
| T991 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.1008855135 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
14954390 ps |
| T992 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.2149706344 |
|
|
Mar 14 12:28:11 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
549186382 ps |
| T993 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2235701325 |
|
|
Mar 14 12:28:03 PM PDT 24 |
Mar 14 12:28:30 PM PDT 24 |
14869179877 ps |
| T994 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2050527642 |
|
|
Mar 14 12:28:40 PM PDT 24 |
Mar 14 12:28:43 PM PDT 24 |
228151807 ps |
| T995 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.33932931 |
|
|
Mar 14 12:28:07 PM PDT 24 |
Mar 14 12:28:07 PM PDT 24 |
42088168 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1637034013 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
36141158 ps |
| T997 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.810328564 |
|
|
Mar 14 12:28:18 PM PDT 24 |
Mar 14 12:28:22 PM PDT 24 |
398643868 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.790070313 |
|
|
Mar 14 12:27:58 PM PDT 24 |
Mar 14 12:27:58 PM PDT 24 |
16644746 ps |
| T999 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1887797380 |
|
|
Mar 14 12:28:12 PM PDT 24 |
Mar 14 12:28:15 PM PDT 24 |
1512316204 ps |
| T89 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.826574632 |
|
|
Mar 14 12:28:15 PM PDT 24 |
Mar 14 12:28:16 PM PDT 24 |
18237314 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.589131541 |
|
|
Mar 14 12:28:09 PM PDT 24 |
Mar 14 12:28:11 PM PDT 24 |
294992415 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.1378886645 |
|
|
Mar 14 12:28:01 PM PDT 24 |
Mar 14 12:28:03 PM PDT 24 |
19103854 ps |
| T1001 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1225136436 |
|
|
Mar 14 12:28:16 PM PDT 24 |
Mar 14 12:28:17 PM PDT 24 |
31030361 ps |
| T1002 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1792109509 |
|
|
Mar 14 12:28:03 PM PDT 24 |
Mar 14 12:28:07 PM PDT 24 |
138043345 ps |
| T90 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.63563047 |
|
|
Mar 14 12:27:47 PM PDT 24 |
Mar 14 12:27:54 PM PDT 24 |
158211027 ps |
| T1003 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.1569175823 |
|
|
Mar 14 12:28:13 PM PDT 24 |
Mar 14 12:28:17 PM PDT 24 |
510049501 ps |
| T91 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3759322883 |
|
|
Mar 14 12:28:10 PM PDT 24 |
Mar 14 12:28:55 PM PDT 24 |
25308827282 ps |
| T1004 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.301367070 |
|
|
Mar 14 12:28:20 PM PDT 24 |
Mar 14 12:28:23 PM PDT 24 |
222642596 ps |
| T92 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.354340155 |
|
|
Mar 14 12:28:02 PM PDT 24 |
Mar 14 12:28:02 PM PDT 24 |
46026366 ps |
| T1005 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3284195303 |
|
|
Mar 14 12:28:29 PM PDT 24 |
Mar 14 12:29:00 PM PDT 24 |
15420662520 ps |
| T1006 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1196547333 |
|
|
Mar 14 12:29:16 PM PDT 24 |
Mar 14 12:29:42 PM PDT 24 |
7564512823 ps |
| T1007 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1452179075 |
|
|
Mar 14 12:28:16 PM PDT 24 |
Mar 14 12:28:17 PM PDT 24 |
23840923 ps |