Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15880123	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153127567

1

T1

704

T2

5790

T3

98303

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83237987	1			T1	1916		T2	3137		T3	32768
values[0x0]	41297298	1			T1	655		T2	1599		T3	32609
values[0x1]	44472405	1			T1	1255		T2	1652		T3	32926

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8080526	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

160927164

1

T1

2300

T2

6097

T3

98303

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	589742	1			T1	2		T2	28		T3	346
valid_sources[0x01]	565919	1			T1	8		T2	21		T3	330
valid_sources[0x02]	1065366	1			T1	17		T2	20		T3	351
valid_sources[0x03]	669117	1			T1	12		T2	20		T3	357
valid_sources[0x04]	707939	1			T1	2		T2	26		T3	407
valid_sources[0x05]	554198	1			T1	23		T2	25		T3	407
valid_sources[0x06]	692114	1			T1	19		T2	28		T3	324
valid_sources[0x07]	748754	1			T1	10		T2	30		T3	391
valid_sources[0x08]	552671	1			T1	22		T2	22		T3	386
valid_sources[0x09]	1622913	1			T1	33		T2	30		T3	394
valid_sources[0x0a]	1942524	1			T1	6		T2	24		T3	372
valid_sources[0x0b]	576304	1			T1	4		T2	31		T3	423
valid_sources[0x0c]	582175	1			T1	11		T2	24		T3	389
valid_sources[0x0d]	585166	1			T1	29		T2	22		T3	377
valid_sources[0x0e]	568957	1			T1	5		T2	29		T3	339
valid_sources[0x0f]	584946	1			T1	8		T2	28		T3	381
valid_sources[0x10]	571814	1			T1	3		T2	21		T3	438
valid_sources[0x11]	579373	1			T1	14		T2	35		T3	356
valid_sources[0x12]	1661739	1			T1	19		T2	21		T3	410
valid_sources[0x13]	589724	1			T1	3		T2	24		T3	339
valid_sources[0x14]	572550	1			T1	22		T2	22		T3	386
valid_sources[0x15]	629609	1			T1	8		T2	23		T3	350
valid_sources[0x16]	589437	1			T1	14		T2	25		T3	466
valid_sources[0x17]	1027108	1			T1	12		T2	33		T3	380
valid_sources[0x18]	550062	1			T1	9		T2	30		T3	395
valid_sources[0x19]	759638	1			T1	5		T2	23		T3	329
valid_sources[0x1a]	1824702	1			T1	1		T2	25		T3	387
valid_sources[0x1b]	554255	1			T1	14		T2	26		T3	365
valid_sources[0x1c]	588653	1			T1	5		T2	17		T3	384
valid_sources[0x1d]	588661	1			T1	14		T2	24		T3	389
valid_sources[0x1e]	577971	1			T1	10		T2	18		T3	380
valid_sources[0x1f]	586576	1			T1	14		T2	27		T3	461
valid_sources[0x20]	561775	1			T1	10		T2	28		T3	357
valid_sources[0x21]	633473	1			T1	40		T2	28		T3	428
valid_sources[0x22]	569758	1			T1	5		T2	31		T3	406
valid_sources[0x23]	569853	1			T1	10		T2	18		T3	377
valid_sources[0x24]	1158534	1			T1	2		T2	14		T3	410
valid_sources[0x25]	571025	1			T1	7		T2	19		T3	395
valid_sources[0x26]	636178	1			T1	11		T2	26		T3	434
valid_sources[0x27]	656010	1			T1	17		T2	27		T3	363
valid_sources[0x28]	563819	1			T1	35		T2	26		T3	411
valid_sources[0x29]	582696	1			T1	11		T2	22		T3	383
valid_sources[0x2a]	572855	1			T1	26		T2	22		T3	347
valid_sources[0x2b]	604386	1			T1	7		T2	28		T3	373
valid_sources[0x2c]	652994	1			T1	24		T2	19		T3	449
valid_sources[0x2d]	551565	1			T1	11		T2	26		T3	372
valid_sources[0x2e]	580240	1			T1	11		T2	20		T3	351
valid_sources[0x2f]	570158	1			T1	1		T2	26		T3	401
valid_sources[0x30]	627363	1			T1	10		T2	20		T3	351
valid_sources[0x31]	566295	1			T1	3		T2	28		T3	467
valid_sources[0x32]	614399	1			T1	3		T2	24		T3	415
valid_sources[0x33]	553498	1			T1	2		T2	27		T3	389
valid_sources[0x34]	607895	1			T1	6		T2	24		T3	340
valid_sources[0x35]	557518	1			T1	6		T2	22		T3	370
valid_sources[0x36]	565407	1			T1	13		T2	28		T3	420
valid_sources[0x37]	652782	1			T2	24		T3	339		T10	766
valid_sources[0x38]	614362	1			T1	3		T2	26		T3	389
valid_sources[0x39]	550770	1			T1	40		T2	22		T3	365
valid_sources[0x3a]	578100	1			T1	6		T2	24		T3	387
valid_sources[0x3b]	585651	1			T1	16		T2	30		T3	351
valid_sources[0x3c]	568280	1			T1	32		T2	23		T3	407
valid_sources[0x3d]	569704	1			T1	26		T2	25		T3	409
valid_sources[0x3e]	585921	1			T1	4		T2	12		T3	423
valid_sources[0x3f]	581543	1			T1	18		T2	22		T3	356
valid_sources[0x40]	557369	1			T1	35		T2	27		T3	399
valid_sources[0x41]	559970	1			T1	32		T2	27		T3	378
valid_sources[0x42]	642452	1			T1	12		T2	25		T3	378
valid_sources[0x43]	583666	1			T1	30		T2	28		T3	358
valid_sources[0x44]	638306	1			T1	12		T2	26		T3	353
valid_sources[0x45]	550391	1			T1	5		T2	23		T3	393
valid_sources[0x46]	584809	1			T1	14		T2	23		T3	429
valid_sources[0x47]	617406	1			T1	2		T2	20		T3	360
valid_sources[0x48]	632965	1			T1	26		T2	28		T3	396
valid_sources[0x49]	563560	1			T1	21		T2	30		T3	404
valid_sources[0x4a]	576478	1			T1	6		T2	18		T3	373
valid_sources[0x4b]	593827	1			T1	13		T2	19		T3	381
valid_sources[0x4c]	563644	1			T1	6		T2	27		T3	427
valid_sources[0x4d]	579147	1			T1	8		T2	26		T3	475
valid_sources[0x4e]	559476	1			T1	8		T2	25		T3	373
valid_sources[0x4f]	623618	1			T1	12		T2	21		T3	412
valid_sources[0x50]	563205	1			T1	5		T2	28		T3	396
valid_sources[0x51]	550315	1			T1	9		T2	30		T3	418
valid_sources[0x52]	915389	1			T1	5		T2	23		T3	331
valid_sources[0x53]	585495	1			T1	31		T2	25		T3	360
valid_sources[0x54]	571180	1			T1	29		T2	36		T3	395
valid_sources[0x55]	582550	1			T2	25		T3	418		T10	809
valid_sources[0x56]	624710	1			T1	38		T2	23		T3	325
valid_sources[0x57]	1120650	1			T1	10		T2	15		T3	369
valid_sources[0x58]	595397	1			T1	17		T2	29		T3	354
valid_sources[0x59]	1702195	1			T1	12		T2	29		T3	429
valid_sources[0x5a]	971443	1			T1	77		T2	26		T3	359
valid_sources[0x5b]	662376	1			T1	42		T2	30		T3	442
valid_sources[0x5c]	592162	1			T1	15		T2	41		T3	437
valid_sources[0x5d]	559133	1			T1	6		T2	22		T3	366
valid_sources[0x5e]	762407	1			T1	3		T2	23		T3	428
valid_sources[0x5f]	585050	1			T1	6		T2	36		T3	361
valid_sources[0x60]	644861	1			T1	32		T2	23		T3	367
valid_sources[0x61]	598573	1			T1	11		T2	24		T3	376
valid_sources[0x62]	552109	1			T1	11		T2	24		T3	359
valid_sources[0x63]	845728	1			T1	13		T2	30		T3	407
valid_sources[0x64]	624390	1			T1	17		T2	21		T3	319
valid_sources[0x65]	581638	1			T1	4		T2	18		T3	410
valid_sources[0x66]	555137	1			T2	25		T3	387		T10	747
valid_sources[0x67]	560516	1			T1	17		T2	28		T3	364
valid_sources[0x68]	560449	1			T1	13		T2	24		T3	377
valid_sources[0x69]	574272	1			T1	15		T2	19		T3	392
valid_sources[0x6a]	620694	1			T1	20		T2	31		T3	348
valid_sources[0x6b]	597080	1			T1	21		T2	30		T3	400
valid_sources[0x6c]	555890	1			T1	11		T2	22		T3	346
valid_sources[0x6d]	556224	1			T1	15		T2	21		T3	426
valid_sources[0x6e]	571532	1			T1	37		T2	23		T3	393
valid_sources[0x6f]	681198	1			T1	5		T2	24		T3	415
valid_sources[0x70]	592283	1			T1	14		T2	22		T3	453
valid_sources[0x71]	640425	1			T1	12		T2	22		T3	413
valid_sources[0x72]	572644	1			T2	31		T3	362		T10	784
valid_sources[0x73]	567457	1			T1	41		T2	26		T3	364
valid_sources[0x74]	554385	1			T1	6		T2	21		T3	409
valid_sources[0x75]	553953	1			T1	9		T2	26		T3	415
valid_sources[0x76]	716803	1			T1	2		T2	26		T3	422
valid_sources[0x77]	570133	1			T1	22		T2	25		T3	440
valid_sources[0x78]	636559	1			T1	23		T2	19		T3	333
valid_sources[0x79]	552979	1			T1	20		T2	26		T3	374
valid_sources[0x7a]	593203	1			T1	12		T2	18		T3	358
valid_sources[0x7b]	572938	1			T1	6		T2	27		T3	409
valid_sources[0x7c]	558158	1			T1	13		T2	20		T3	416
valid_sources[0x7d]	560642	1			T1	8		T2	23		T3	352
valid_sources[0x7e]	639776	1			T1	10		T2	24		T3	324
valid_sources[0x7f]	575684	1			T1	20		T2	25		T3	347
valid_sources[0x80]	647275	1			T1	44		T2	25		T3	364

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75252294

1

T1

342

T2

2835

T3

32768

values[0x0]

all_enables

biggest_size

38930739

1

T1

186

T2

1524

T3

32609

values[0x1]

all_enables

biggest_size

38944534

1

T1

176

T2

1431

T3

32926

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33102	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156360

1

T1

1

T5

1420

T9

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54229	1			T5	428		T6	14		T7	21
values[0x0]	65527	1			T1	2		T5	538		T9	9
values[0x1]	69706	1			T2	2		T5	555		T9	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24788	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164674

1

T1

1

T5

1472

T9

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	967	1			T5	2		T18	1		T47	1
valid_sources[0x01]	776	1			T5	7		T9	1		T8	1
valid_sources[0x02]	660	1			T5	5		T6	1		T131	1
valid_sources[0x03]	865	1			T7	1		T8	1		T87	1
valid_sources[0x04]	865	1			T5	11		T21	1		T47	2
valid_sources[0x05]	757	1			T5	9		T7	2		T8	1
valid_sources[0x06]	659	1			T8	1		T47	2		T132	1
valid_sources[0x07]	528	1			T5	11		T8	3		T18	1
valid_sources[0x08]	702	1			T8	2		T47	2		T116	1
valid_sources[0x09]	1044	1			T5	20		T8	1		T18	2
valid_sources[0x0a]	570	1			T5	1		T8	3		T133	1
valid_sources[0x0b]	572	1			T5	2		T18	7		T30	1
valid_sources[0x0c]	853	1			T5	14		T18	3		T32	1
valid_sources[0x0d]	646	1			T18	1		T23	7		T47	6
valid_sources[0x0e]	768	1			T5	2		T47	6		T48	9
valid_sources[0x0f]	767	1			T5	10		T8	2		T18	6
valid_sources[0x10]	838	1			T18	1		T47	5		T116	1
valid_sources[0x11]	740	1			T5	3		T21	1		T8	1
valid_sources[0x12]	651	1			T5	29		T8	1		T18	1
valid_sources[0x13]	659	1			T5	6		T8	1		T133	3
valid_sources[0x14]	758	1			T5	9		T47	10		T48	3
valid_sources[0x15]	514	1			T5	12		T8	1		T134	9
valid_sources[0x16]	493	1			T5	2		T18	16		T29	1
valid_sources[0x17]	667	1			T5	9		T8	4		T30	2
valid_sources[0x18]	848	1			T5	1		T21	1		T8	2
valid_sources[0x19]	649	1			T5	5		T45	1		T19	1
valid_sources[0x1a]	815	1			T47	1		T48	8		T124	4
valid_sources[0x1b]	836	1			T5	4		T7	1		T8	2
valid_sources[0x1c]	965	1			T5	2		T8	3		T18	2
valid_sources[0x1d]	868	1			T30	11		T32	1		T47	2
valid_sources[0x1e]	901	1			T5	1		T27	1		T44	2
valid_sources[0x1f]	938	1			T18	1		T54	1		T47	4
valid_sources[0x20]	1186	1			T5	1		T6	1		T18	1
valid_sources[0x21]	734	1			T7	2		T8	1		T47	8
valid_sources[0x22]	948	1			T5	1		T11	1		T8	1
valid_sources[0x23]	848	1			T9	2		T8	1		T47	6
valid_sources[0x24]	591	1			T5	1		T19	1		T31	1
valid_sources[0x25]	771	1			T8	2		T18	16		T47	1
valid_sources[0x26]	711	1			T5	12		T9	2		T8	1
valid_sources[0x27]	696	1			T5	8		T8	1		T18	8
valid_sources[0x28]	841	1			T5	7		T8	4		T18	2
valid_sources[0x29]	604	1			T5	11		T7	1		T8	2
valid_sources[0x2a]	513	1			T5	17		T8	1		T30	5
valid_sources[0x2b]	662	1			T5	7		T8	2		T30	2
valid_sources[0x2c]	1379	1			T18	1		T54	1		T47	2
valid_sources[0x2d]	1181	1			T5	1		T8	1		T30	3
valid_sources[0x2e]	588	1			T5	12		T7	1		T8	1
valid_sources[0x2f]	1183	1			T5	6		T8	1		T47	8
valid_sources[0x30]	866	1			T8	1		T32	1		T47	8
valid_sources[0x31]	1056	1			T5	22		T54	1		T47	4
valid_sources[0x32]	582	1			T5	3		T8	3		T135	2
valid_sources[0x33]	540	1			T7	1		T8	2		T40	1
valid_sources[0x34]	655	1			T8	1		T18	6		T47	5
valid_sources[0x35]	815	1			T5	13		T8	2		T87	1
valid_sources[0x36]	510	1			T2	1		T5	2		T9	3
valid_sources[0x37]	1002	1			T5	13		T8	4		T18	5
valid_sources[0x38]	653	1			T5	5		T30	2		T47	6
valid_sources[0x39]	684	1			T5	7		T9	1		T7	2
valid_sources[0x3a]	763	1			T5	1		T8	1		T30	71
valid_sources[0x3b]	552	1			T8	1		T18	12		T47	1
valid_sources[0x3c]	783	1			T2	1		T5	2		T45	1
valid_sources[0x3d]	855	1			T18	10		T22	5		T19	1
valid_sources[0x3e]	626	1			T5	2		T54	1		T47	7
valid_sources[0x3f]	632	1			T5	27		T18	1		T47	5
valid_sources[0x40]	591	1			T5	9		T8	2		T32	1
valid_sources[0x41]	665	1			T18	11		T47	1		T48	18
valid_sources[0x42]	1073	1			T5	4		T7	1		T8	1
valid_sources[0x43]	559	1			T45	2		T18	12		T19	1
valid_sources[0x44]	481	1			T5	22		T8	1		T87	1
valid_sources[0x45]	824	1			T5	6		T18	14		T69	1
valid_sources[0x46]	651	1			T5	3		T14	5		T21	1
valid_sources[0x47]	595	1			T22	1		T29	1		T30	1
valid_sources[0x48]	936	1			T5	2		T8	2		T18	16
valid_sources[0x49]	640	1			T5	3		T7	1		T8	3
valid_sources[0x4a]	567	1			T5	5		T41	1		T54	1
valid_sources[0x4b]	841	1			T5	9		T18	8		T29	1
valid_sources[0x4c]	633	1			T5	1		T47	1		T24	3
valid_sources[0x4d]	736	1			T5	6		T29	2		T47	14
valid_sources[0x4e]	882	1			T14	1		T8	3		T18	9
valid_sources[0x4f]	634	1			T5	9		T47	14		T116	1
valid_sources[0x50]	727	1			T5	4		T47	6		T33	1
valid_sources[0x51]	801	1			T5	21		T8	1		T47	1
valid_sources[0x52]	639	1			T5	7		T26	1		T8	1
valid_sources[0x53]	650	1			T5	4		T8	1		T47	7
valid_sources[0x54]	1062	1			T5	10		T9	2		T21	1
valid_sources[0x55]	807	1			T5	5		T8	2		T18	1
valid_sources[0x56]	879	1			T5	5		T30	3		T47	1
valid_sources[0x57]	602	1			T5	3		T6	1		T47	8
valid_sources[0x58]	546	1			T6	2		T7	1		T136	1
valid_sources[0x59]	793	1			T5	20		T8	2		T29	2
valid_sources[0x5a]	783	1			T5	12		T8	1		T18	33
valid_sources[0x5b]	773	1			T5	2		T17	1		T45	1
valid_sources[0x5c]	532	1			T5	5		T45	1		T30	1
valid_sources[0x5d]	621	1			T5	1		T27	1		T32	1
valid_sources[0x5e]	624	1			T18	1		T47	1		T20	1
valid_sources[0x5f]	1034	1			T9	3		T8	3		T137	1
valid_sources[0x60]	925	1			T5	8		T27	2		T47	8
valid_sources[0x61]	623	1			T5	5		T26	2		T8	1
valid_sources[0x62]	731	1			T5	5		T31	1		T47	4
valid_sources[0x63]	473	1			T18	2		T19	1		T32	1
valid_sources[0x64]	931	1			T5	3		T8	2		T18	3
valid_sources[0x65]	509	1			T5	2		T8	1		T30	2
valid_sources[0x66]	509	1			T18	3		T47	4		T24	1
valid_sources[0x67]	643	1			T5	13		T8	1		T47	9
valid_sources[0x68]	711	1			T18	1		T30	4		T47	10
valid_sources[0x69]	615	1			T5	9		T8	1		T18	9
valid_sources[0x6a]	1018	1			T8	2		T30	1		T47	5
valid_sources[0x6b]	553	1			T18	3		T134	1		T41	2
valid_sources[0x6c]	631	1			T7	1		T8	1		T47	10
valid_sources[0x6d]	812	1			T5	3		T9	3		T18	2
valid_sources[0x6e]	745	1			T5	30		T32	2		T47	7
valid_sources[0x6f]	792	1			T5	13		T8	2		T136	1
valid_sources[0x70]	718	1			T5	4		T27	1		T41	2
valid_sources[0x71]	921	1			T5	8		T7	1		T18	15
valid_sources[0x72]	601	1			T5	2		T21	1		T8	2
valid_sources[0x73]	498	1			T8	2		T54	1		T47	2
valid_sources[0x74]	683	1			T5	16		T7	1		T8	1
valid_sources[0x75]	577	1			T8	1		T18	17		T47	11
valid_sources[0x76]	549	1			T8	2		T54	3		T47	12
valid_sources[0x77]	733	1			T5	3		T30	1		T47	2
valid_sources[0x78]	926	1			T5	8		T6	1		T32	1
valid_sources[0x79]	1017	1			T5	14		T7	1		T8	4
valid_sources[0x7a]	756	1			T5	2		T21	1		T16	1
valid_sources[0x7b]	541	1			T5	3		T8	1		T47	2
valid_sources[0x7c]	590	1			T5	3		T47	5		T48	4
valid_sources[0x7d]	778	1			T5	1		T26	3		T8	1
valid_sources[0x7e]	648	1			T8	1		T18	10		T47	3
valid_sources[0x7f]	921	1			T5	2		T7	1		T8	1
valid_sources[0x80]	942	1			T5	3		T8	1		T88	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42335

1

T5

387

T6

9

T7

12

values[0x0]

all_enables

biggest_size

57957

1

T1

1

T5

533

T9

2

values[0x1]

all_enables

biggest_size

56068

1

T5

500

T12

1

T14

2