Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15783191

1

T1

3122

T2

598

T5

2465

full_word

149844501

1

T1

704

T2

5790

T3

98303

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	165627422	1			T1	3826		T2	6388		T3	98303
auto[TlIntgErrCmd]	89	1			T94	6		T95	3		T96	7
auto[TlIntgErrData]	92	1			T94	3		T95	3		T96	5
auto[TlIntgErrBoth]	89	1			T94	1		T95	4		T96	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79747320

1

T1

1916

T2

3137

T3

32768

auto[1]

85880372

1

T1

1910

T2

3251

T3

65535

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7710184	1			T1	1574		T2	302		T5	489
auto[TlIntgErrNone]	partial	auto[1]	8072764	1			T1	1548		T2	296		T5	1976
auto[TlIntgErrNone]	full_word	auto[0]	72037015	1			T1	342		T2	2835		T3	32768
auto[TlIntgErrNone]	full_word	auto[1]	77807459	1			T1	362		T2	2955		T3	65535
auto[TlIntgErrCmd]	partial	auto[0]	38	1			T94	2		T95	1		T96	3
auto[TlIntgErrCmd]	partial	auto[1]	46	1			T94	4		T95	2		T96	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T104	1		T112	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T114	1		T115	1		-	-
auto[TlIntgErrData]	partial	auto[0]	41	1			T94	1		T95	2		T96	3
auto[TlIntgErrData]	partial	auto[1]	40	1			T94	2		T95	1		T96	1
auto[TlIntgErrData]	full_word	auto[0]	3	1			T103	2		T105	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	8	1			T96	1		T103	1		T104	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1			T94	1		T95	1		T96	2
auto[TlIntgErrBoth]	partial	auto[1]	47	1			T95	1		T96	5		T106	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1			T95	1		T96	1		T114	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T95	1		T106	1		T110	1