Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	783945	1			T1	470		T10	22751		T6	14
auto[1]	10499996	1			T1	432		T2	1		T4	417
auto[2]	607353	1			T1	318		T10	16228		T6	10
auto[3]	10226998	1			T1	305		T4	408		T10	13293

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14460626	1			T1	31		T2	1		T4	589
auto[1]	1973632	1			T1	218		T4	104		T10	10321
auto[2]	2003944	1			T1	189		T4	112		T10	8446
auto[3]	3680090	1			T1	1087		T4	20		T10	51377

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9588519

1

T1

1525

T2

1

T4

825

auto[1]

12529773

1

T10

71845

T14

1

T45

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	286433	1			T1	15		T6	12		T17	1
auto[0]	auto[0]	auto[1]	30995	1			T1	75		T6	1		T45	481
auto[0]	auto[0]	auto[2]	30988	1			T1	71		T6	1		T17	1
auto[0]	auto[0]	auto[3]	116470	1			T1	309		T45	46		T66	2140
auto[0]	auto[1]	auto[0]	3283732	1			T1	3		T2	1		T4	303
auto[0]	auto[1]	auto[1]	346024	1			T1	75		T4	48		T11	20
auto[0]	auto[1]	auto[2]	366270	1			T1	16		T4	56		T11	83
auto[0]	auto[1]	auto[3]	507989	1			T1	338		T4	10		T11	1969
auto[0]	auto[2]	auto[0]	206364	1			T1	12		T6	9		T45	2867
auto[0]	auto[2]	auto[1]	30135	1			T1	57		T17	1		T45	279
auto[0]	auto[2]	auto[2]	21613	1			T1	39		T6	1		T45	437
auto[0]	auto[2]	auto[3]	80426	1			T1	210		T17	1		T45	47
auto[0]	auto[3]	auto[0]	3122422	1			T1	1		T4	286		T11	16
auto[0]	auto[3]	auto[1]	344949	1			T1	11		T4	56		T11	68
auto[0]	auto[3]	auto[2]	361657	1			T1	63		T4	56		T11	216
auto[0]	auto[3]	auto[3]	452052	1			T1	230		T4	10		T11	1816
auto[1]	auto[0]	auto[0]	10447	1			T10	792		T45	1		T28	1
auto[1]	auto[0]	auto[1]	47799	1			T10	3465		T129	2310		T130	2649
auto[1]	auto[0]	auto[2]	47260	1			T10	3329		T129	2228		T130	2590
auto[1]	auto[0]	auto[3]	213553	1			T10	15165		T66	3		T70	1
auto[1]	auto[1]	auto[0]	3772167	1			T10	111		T8	1		T87	201
auto[1]	auto[1]	auto[1]	588421	1			T10	3409		T87	2624		T88	2985
auto[1]	auto[1]	auto[2]	554638	1			T10	575		T87	896		T88	3389
auto[1]	auto[1]	auto[3]	1080755	1			T10	15478		T87	12112		T88	294
auto[1]	auto[2]	auto[0]	8605	1			T10	733		T45	1		T28	1
auto[1]	auto[2]	auto[1]	38602	1			T10	3107		T28	1		T129	2059
auto[1]	auto[2]	auto[2]	40345	1			T10	2269		T129	1982		T130	2778
auto[1]	auto[2]	auto[3]	181263	1			T10	10119		T129	8551		T130	12781
auto[1]	auto[3]	auto[0]	3770456	1			T10	65		T14	1		T8	2
auto[1]	auto[3]	auto[1]	546707	1			T10	340		T87	821		T88	3428
auto[1]	auto[3]	auto[2]	581173	1			T10	2273		T87	2657		T88	3049
auto[1]	auto[3]	auto[3]	1047582	1			T10	10615		T87	12287		T69	1