Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1086675658	151670	0	0
ctrl_regwen_rd_A	1086675658	6862	0	0
exec_rd_A	1086675658	6405	0	0
exec_regwen_rd_A	1086675658	7077	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086675658	151670	0	0
T4	67622	0	0	0
T5	41958	1011	0	0
T6	470972	0	0	0
T9	1096	0	0	0
T10	163817	0	0	0
T11	234675	0	0	0
T12	1212	0	0	0
T13	73797	0	0	0
T14	605356	0	0	0
T15	197285	0	0	0
T18	0	867	0	0
T30	0	1474	0	0
T47	0	1619	0	0
T48	0	1092	0	0
T49	0	669	0	0
T50	0	4708	0	0
T51	0	2805	0	0
T52	0	613	0	0
T53	0	5150	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086675658	6862	0	0
T4	67622	0	0	0
T5	41958	288	0	0
T6	470972	0	0	0
T9	1096	0	0	0
T10	163817	0	0	0
T11	234675	0	0	0
T12	1212	0	0	0
T13	73797	0	0	0
T14	605356	0	0	0
T15	197285	0	0	0
T30	0	462	0	0
T47	0	307	0	0
T49	0	181	0	0
T97	0	281	0	0
T98	0	490	0	0
T99	0	393	0	0
T100	0	120	0	0
T101	0	496	0	0
T102	0	685	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086675658	6405	0	0
T4	67622	0	0	0
T5	41958	231	0	0
T6	470972	0	0	0
T9	1096	0	0	0
T10	163817	0	0	0
T11	234675	0	0	0
T12	1212	0	0	0
T13	73797	0	0	0
T14	605356	0	0	0
T15	197285	0	0	0
T30	0	328	0	0
T47	0	312	0	0
T49	0	199	0	0
T97	0	232	0	0
T98	0	491	0	0
T99	0	346	0	0
T100	0	144	0	0
T101	0	519	0	0
T102	0	784	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1086675658	7077	0	0
T4	67622	0	0	0
T5	41958	340	0	0
T6	470972	0	0	0
T9	1096	0	0	0
T10	163817	0	0	0
T11	234675	0	0	0
T12	1212	0	0	0
T13	73797	0	0	0
T14	605356	0	0	0
T15	197285	0	0	0
T30	0	299	0	0
T47	0	403	0	0
T49	0	216	0	0
T97	0	316	0	0
T98	0	586	0	0
T99	0	409	0	0
T100	0	127	0	0
T101	0	419	0	0
T102	0	648	0	0