Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.99	100.00	90.74		100.00	84.21	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul_adapter_sram.u_sram_byte	100.00	100.00	100.00		100.00	100.00	100.00

---

Module Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.77	100.00	95.10			100.00	100.00	u_tlul_adapter_sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_integ_handling.u_sync_fifo	100.00	100.00	100.00			100.00	100.00
gen_integ_handling.u_sync_fifo_a_size	100.00	100.00	100.00			100.00	100.00
gen_integ_handling.u_tlul_data_integ_enc	100.00	100.00

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		64	64	100.00
ALWAYS	56	3	3	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	84	20	20	100.00
CONT_ASSIGN	145	1	1	100.00
ALWAYS	178	2	2	100.00
ALWAYS	189	0	0
ALWAYS	189	2	2	100.00
ALWAYS	208	2	2	100.00
ALWAYS	215	20	20	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	291	4	4	100.00
CONT_ASSIGN	309	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
59	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
79	1	1
80	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
			MISSING_ELSE
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
			==> MISSING_ELSE
			MISSING_ELSE
115	1	1
116	1	1
118	1	1
119	1	1
			==> MISSING_ELSE
145	1	1
178	1	1
179	1	1
			MISSING_ELSE
189	1	1
190	1	1
208	1	1
209	1	1
215	1	1
217	1	1
226	1	1
227	1	1
228	1	1
231	1	1
232	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
244	1	1
246	1	1
249	1	1
250	1	1
252	1	1
253	1	1
			MISSING_ELSE
			MISSING_ELSE
262	1	1
266	1	1
291	1	1
294	1	1
298	1	1
303	1	1
309	1	1

---

Cond Coverage for Module : tlul_sram_byte

	Total	Covered	Percent
Conditions	54	49	90.74
Logical	54	49	90.74
Non-Logical	0	0
Event	0	0

 LINE       73
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T6
1	1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       77
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       77
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T5,T8,T18
1	1	1	Covered	T1,T2,T4

 LINE       80
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       106
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T10,T6
1	Covered	T1,T2,T4

 LINE       178
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       190
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       217
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait)
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T10
1	0	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T18
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       252
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       266
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T14,T19,T20
1	0	1	1	Not Covered
1	1	0	1	Not Covered
1	1	1	0	Not Covered
1	1	1	1	Covered	T1,T2,T3

 LINE       298
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)))
             --------1--------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

FSM Coverage for Module : tlul_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	3	3	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StPassThru	119	Covered	T1,T2,T3
StWaitRd	95	Covered	T1,T2,T4
StWriteCmd	109	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StPassThru->StWaitRd	95	Covered	T1,T2,T4
StWaitRd->StWriteCmd	109	Covered	T1,T2,T4
StWriteCmd->StPassThru	119	Covered	T1,T2,T4

---

Branch Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
Branches		19	16	84.21
IF	56	2	2	100.00
CASE	90	9	6	66.67
IF	178	2	2	100.00
TERNARY	190	2	2	100.00
IF	226	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	56	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	case (gen_integ_handling.state_q)
-2-:	92	if (gen_integ_handling.byte_wr_txn)
-3-:	94	if (gen_integ_handling.byte_req_ack)
-4-:	106	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-5-:	108	if (gen_integ_handling.sram_d_ack)
-6-:	118	if (gen_integ_handling.sram_a_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
StPassThru	1	1	-	-	-	Covered	T1,T2,T4
StPassThru	1	0	-	-	-	Covered	T1,T5,T10
StPassThru	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	1	1	-	Covered	T1,T2,T4
StWaitRd	-	-	1	0	-	Not Covered
StWaitRd	-	-	0	-	-	Covered	T1,T10,T6
StWriteCmd	-	-	-	-	1	Covered	T1,T2,T4
StWriteCmd	-	-	-	-	0	Not Covered
default	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	178	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	226	if (gen_integ_handling.wr_phase)
-2-:	242	if (gen_integ_handling.rd_phase)
-3-:	246	if (((!error_i) || gen_integ_handling.stall_host))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T4
0	1	1	Covered	T1,T2,T4
0	1	0	Covered	T5,T8,T18
0	0	-	Covered	T1,T2,T3

---

Assert Coverage for Module : tlul_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_integ_handling.ByteAccessStateChange_A	1074008205	7139345	0	0
gen_integ_handling.ReadCompleteStateChange_A	1074008205	7139345	0	0
gen_integ_handling.TlulSramByteTlSize_A	1074008205	1073887468	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	7139345	0	0
T1	95093	1548	0	0
T2	113331	296	0	0
T3	197862	0	0	0
T4	67622	66	0	0
T5	41958	0	0	0
T6	470972	2	0	0
T9	1096	0	0	0
T10	163817	81245	0	0
T11	234675	14771	0	0
T12	1212	0	0	0
T13	0	540	0	0
T14	0	3003	0	0
T16	0	29826	0	0
T17	0	4028	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	7139345	0	0
T1	95093	1548	0	0
T2	113331	296	0	0
T3	197862	0	0	0
T4	67622	66	0	0
T5	41958	0	0	0
T6	470972	2	0	0
T9	1096	0	0	0
T10	163817	81245	0	0
T11	234675	14771	0	0
T12	1212	0	0	0
T13	0	540	0	0
T14	0	3003	0	0
T16	0	29826	0	0
T17	0	4028	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	1073887468	0	0
T1	95093	95030	0	0
T2	113331	113264	0	0
T3	197862	197796	0	0
T4	67622	67572	0	0
T5	41958	41773	0	0
T6	470972	470852	0	0
T9	1096	1031	0	0
T10	163817	163809	0	0
T11	234675	234621	0	0
T12	1212	1145	0	0

Line Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		64	64	100.00
ALWAYS	56	3	3	100.00
CONT_ASSIGN	73	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	80	1	1	100.00
ALWAYS	84	20	20	100.00
CONT_ASSIGN	145	1	1	100.00
ALWAYS	178	2	2	100.00
ALWAYS	189	0	0
ALWAYS	189	2	2	100.00
ALWAYS	208	2	2	100.00
ALWAYS	215	20	20	100.00
CONT_ASSIGN	262	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
ALWAYS	291	4	4	100.00
CONT_ASSIGN	309	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	1	1
57	1	1
59	1	1
73	1	1
74	1	1
75	1	1
76	1	1
77	1	1
79	1	1
80	1	1
84	1	1
85	1	1
86	1	1
87	1	1
88	1	1
90	1	1
92	1	1
93	1	1
94	1	1
95	1	1
			MISSING_ELSE
			MISSING_ELSE
104	1	1
105	1	1
106	1	1
107	1	1
108	1	1
109	1	1
			==> MISSING_ELSE
			MISSING_ELSE
115	1	1
116	1	1
118	1	1
119	1	1
			==> MISSING_ELSE
			Exclude Annotation: VC_COV_UNR
145	1	1
178	1	1
179	1	1
			MISSING_ELSE
189	1	1
190	1	1
208	1	1
209	1	1
215	1	1
217	1	1
226	1	1
227	1	1
228	1	1
231	1	1
232	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
242	1	1
244	1	1
246	1	1
249	1	1
250	1	1
252	1	1
253	1	1
			MISSING_ELSE
			MISSING_ELSE
262	1	1
266	1	1
291	1	1
294	1	1
298	1	1
303	1	1
309	1	1

---

Cond Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Covered	Percent
Conditions	49	49	100.00
Logical	49	49	100.00
Non-Logical	0	0
Event	0	0

 LINE       73
 EXPRESSION (tl_i.a_valid & tl_o.a_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (tl_o.d_valid & tl_i.d_ready)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       75
 EXPRESSION (tl_sram_o.a_valid & tl_sram_i.a_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T10,T6
1	1	Covered	T1,T2,T3

 LINE       76
 EXPRESSION (tl_sram_i.d_valid & tl_sram_o.d_ready)
             --------1--------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       77
 EXPRESSION ((tl_i.a_opcode == PutFullData) | (tl_i.a_opcode == PutPartialData))
             ---------------1--------------   ----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       77
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       77
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       79
 EXPRESSION (gen_integ_handling.byte_wr_txn & gen_integ_handling.a_ack & ((~error_i)))
             ---------------1--------------   ------------2-----------   ------3-----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T4
1	1	0	Covered	T5,T8,T18
1	1	1	Covered	T1,T2,T4

 LINE       80
 EXPRESSION (tl_i.a_valid & ((~&tl_i.a_mask)) & gen_integ_handling.wr_txn)
             ------1-----   --------2--------   ------------3------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T1,T2,T5
1	1	1	Covered	T1,T2,T5

 LINE       106
 EXPRESSION (gen_integ_handling.pending_txn_cnt == 2'(1))
            ----------------------1----------------------

-1-	Status	Tests
0	Covered	T1,T10,T6
1	Covered	T1,T2,T4

 LINE       178
 EXPRESSION (gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait)
             --------------1--------------    -------------2------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       190
 EXPRESSION (gen_integ_handling.held_data.a_mask[i] ? gen_integ_handling.held_data.a_data[(i * 8)+:8] : gen_integ_handling.rsp_data[(i * 8)+:8])
             -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T4
1	Covered	T1,T2,T4

 LINE       217
 EXPRESSION (tl_i.d_ready | gen_integ_handling.rd_wait)
             ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T10
1	0	Covered	T1,T2,T3

 LINE       246
 EXPRESSION (((!error_i)) || gen_integ_handling.stall_host)
             ------1-----    --------------2--------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T8,T18
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T4

 LINE       252
 EXPRESSION (tl_i.a_valid & ((~gen_integ_handling.stall_host)))
             ------1-----   -----------------2----------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T4

 LINE       266
 EXPRESSION (error_i & ((~gen_integ_handling.stall_host)))
             ---1---   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       294
 EXPRESSION (tl_sram_i.a_ready & ((~gen_integ_handling.stall_host)) & gen_integ_handling.fifo_rdy & gen_integ_handling.size_fifo_rdy)
             --------1--------   -----------------2----------------   -------------3-------------   ----------------4---------------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T14,T19,T20
1	0	1	1	Excluded		VC_COV_UNR
1	1	0	1	Excluded		VC_COV_UNR
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       298
 EXPRESSION (tl_sram_i.d_valid & ((~gen_integ_handling.rd_wait)))
             --------1--------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

Summary for FSM :: gen_integ_handling.state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	3	3	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: gen_integ_handling.state_q

---

states	Line No.	Covered	Tests
StPassThru	119	Covered	T1,T2,T3
StWaitRd	95	Covered	T1,T2,T4
StWriteCmd	109	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests
StPassThru->StWaitRd	95	Covered	T1,T2,T4
StWaitRd->StWriteCmd	109	Covered	T1,T2,T4
StWriteCmd->StPassThru	119	Covered	T1,T2,T4

---

Branch Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	56	2	2	100.00
CASE	90	6	6	100.00
IF	178	2	2	100.00
TERNARY	190	2	2	100.00
IF	226	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	56	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	case (gen_integ_handling.state_q)
-2-:	92	if (gen_integ_handling.byte_wr_txn)
-3-:	94	if (gen_integ_handling.byte_req_ack)
-4-:	106	if ((gen_integ_handling.pending_txn_cnt == 2'(1)))
-5-:	108	if (gen_integ_handling.sram_d_ack)
-6-:	118	if (gen_integ_handling.sram_a_ack)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests	Exclude Annotation
StPassThru	1	1	-	-	-	Covered	T1,T2,T4
StPassThru	1	0	-	-	-	Covered	T1,T5,T10
StPassThru	0	-	-	-	-	Covered	T1,T2,T3
StWaitRd	-	-	1	1	-	Covered	T1,T2,T4
StWaitRd	-	-	1	0	-	Excluded		[UNR] this should not happen because the read latency of prim_ram_1p_scr is always 1 cycle
StWaitRd	-	-	0	-	-	Covered	T1,T10,T6
StWriteCmd	-	-	-	-	1	Covered	T1,T2,T4
StWriteCmd	-	-	-	-	0	Excluded		[UNR] this should not happen because prim_ram_1p_scr can always accept a read or write operation
default	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	178	if ((gen_integ_handling.sram_d_ack && gen_integ_handling.rd_wait))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	190	(gen_integ_handling.held_data.a_mask[i]) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T4
0	Covered	T1,T2,T4

	LineNo.	Expression
-1-:	226	if (gen_integ_handling.wr_phase)
-2-:	242	if (gen_integ_handling.rd_phase)
-3-:	246	if (((!error_i) || gen_integ_handling.stall_host))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T4
0	1	1	Covered	T1,T2,T4
0	1	0	Covered	T5,T8,T18
0	0	-	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul_adapter_sram.u_sram_byte

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_integ_handling.ByteAccessStateChange_A	1074008205	7139345	0	0
gen_integ_handling.ReadCompleteStateChange_A	1074008205	7139345	0	0
gen_integ_handling.TlulSramByteTlSize_A	1074008205	1073887468	0	0

gen_integ_handling.ByteAccessStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	7139345	0	0
T1	95093	1548	0	0
T2	113331	296	0	0
T3	197862	0	0	0
T4	67622	66	0	0
T5	41958	0	0	0
T6	470972	2	0	0
T9	1096	0	0	0
T10	163817	81245	0	0
T11	234675	14771	0	0
T12	1212	0	0	0
T13	0	540	0	0
T14	0	3003	0	0
T16	0	29826	0	0
T17	0	4028	0	0

gen_integ_handling.ReadCompleteStateChange_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	7139345	0	0
T1	95093	1548	0	0
T2	113331	296	0	0
T3	197862	0	0	0
T4	67622	66	0	0
T5	41958	0	0	0
T6	470972	2	0	0
T9	1096	0	0	0
T10	163817	81245	0	0
T11	234675	14771	0	0
T12	1212	0	0	0
T13	0	540	0	0
T14	0	3003	0	0
T16	0	29826	0	0
T17	0	4028	0	0

gen_integ_handling.TlulSramByteTlSize_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1074008205	1073887468	0	0
T1	95093	95030	0	0
T2	113331	113264	0	0
T3	197862	197796	0	0
T4	67622	67572	0	0
T5	41958	41773	0	0
T6	470972	470852	0	0
T9	1096	1031	0	0
T10	163817	163809	0	0
T11	234675	234621	0	0
T12	1212	1145	0	0