| T794 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.1942082769 |
|
|
Mar 17 03:09:53 PM PDT 24 |
Mar 17 03:14:47 PM PDT 24 |
4280014198 ps |
| T795 |
/workspace/coverage/default/46.sram_ctrl_stress_all.2949816956 |
|
|
Mar 17 03:11:52 PM PDT 24 |
Mar 17 04:21:52 PM PDT 24 |
121354764245 ps |
| T796 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.4039336168 |
|
|
Mar 17 03:09:57 PM PDT 24 |
Mar 17 03:10:05 PM PDT 24 |
2901536021 ps |
| T797 |
/workspace/coverage/default/0.sram_ctrl_executable.3612296145 |
|
|
Mar 17 03:05:51 PM PDT 24 |
Mar 17 03:32:01 PM PDT 24 |
38805214232 ps |
| T798 |
/workspace/coverage/default/41.sram_ctrl_stress_pipeline.1810519637 |
|
|
Mar 17 03:10:38 PM PDT 24 |
Mar 17 03:15:28 PM PDT 24 |
8776609107 ps |
| T799 |
/workspace/coverage/default/25.sram_ctrl_access_during_key_req.253541633 |
|
|
Mar 17 03:07:45 PM PDT 24 |
Mar 17 03:08:15 PM PDT 24 |
1308734933 ps |
| T800 |
/workspace/coverage/default/43.sram_ctrl_partial_access_b2b.4153763366 |
|
|
Mar 17 03:10:59 PM PDT 24 |
Mar 17 03:14:04 PM PDT 24 |
3843718142 ps |
| T801 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.3512547626 |
|
|
Mar 17 03:09:52 PM PDT 24 |
Mar 17 03:15:54 PM PDT 24 |
59291678836 ps |
| T802 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.1530574479 |
|
|
Mar 17 03:12:06 PM PDT 24 |
Mar 17 03:12:35 PM PDT 24 |
2442225905 ps |
| T803 |
/workspace/coverage/default/37.sram_ctrl_regwen.2488219464 |
|
|
Mar 17 03:09:57 PM PDT 24 |
Mar 17 03:27:09 PM PDT 24 |
43730264920 ps |
| T804 |
/workspace/coverage/default/41.sram_ctrl_regwen.4204846210 |
|
|
Mar 17 03:10:43 PM PDT 24 |
Mar 17 03:42:44 PM PDT 24 |
67540268013 ps |
| T805 |
/workspace/coverage/default/45.sram_ctrl_ram_cfg.1441663212 |
|
|
Mar 17 03:11:34 PM PDT 24 |
Mar 17 03:11:37 PM PDT 24 |
1408270024 ps |
| T806 |
/workspace/coverage/default/14.sram_ctrl_mem_partial_access.1410839761 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:07:41 PM PDT 24 |
1003174708 ps |
| T807 |
/workspace/coverage/default/26.sram_ctrl_stress_all_with_rand_reset.663861044 |
|
|
Mar 17 03:07:56 PM PDT 24 |
Mar 17 03:16:59 PM PDT 24 |
62096430648 ps |
| T808 |
/workspace/coverage/default/17.sram_ctrl_smoke.2343223378 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:07:07 PM PDT 24 |
5214393492 ps |
| T809 |
/workspace/coverage/default/1.sram_ctrl_throughput_w_partial_write.2109976 |
|
|
Mar 17 03:05:59 PM PDT 24 |
Mar 17 03:06:06 PM PDT 24 |
682457729 ps |
| T810 |
/workspace/coverage/default/12.sram_ctrl_multiple_keys.3001923743 |
|
|
Mar 17 03:06:25 PM PDT 24 |
Mar 17 03:14:17 PM PDT 24 |
17859979735 ps |
| T811 |
/workspace/coverage/default/10.sram_ctrl_partial_access.1676414829 |
|
|
Mar 17 03:06:21 PM PDT 24 |
Mar 17 03:06:25 PM PDT 24 |
365573771 ps |
| T812 |
/workspace/coverage/default/10.sram_ctrl_stress_all.1856715617 |
|
|
Mar 17 03:06:22 PM PDT 24 |
Mar 17 04:44:34 PM PDT 24 |
86347220350 ps |
| T813 |
/workspace/coverage/default/16.sram_ctrl_regwen.3228439689 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:26:23 PM PDT 24 |
8994715896 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_bijection.13118195 |
|
|
Mar 17 03:05:56 PM PDT 24 |
Mar 17 03:26:44 PM PDT 24 |
76841059368 ps |
| T815 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.2525945115 |
|
|
Mar 17 03:05:51 PM PDT 24 |
Mar 17 03:10:25 PM PDT 24 |
26048996746 ps |
| T816 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2827017671 |
|
|
Mar 17 03:09:50 PM PDT 24 |
Mar 17 03:24:26 PM PDT 24 |
7285606309 ps |
| T817 |
/workspace/coverage/default/20.sram_ctrl_partial_access_b2b.2319779662 |
|
|
Mar 17 03:07:01 PM PDT 24 |
Mar 17 03:15:51 PM PDT 24 |
22728379095 ps |
| T818 |
/workspace/coverage/default/20.sram_ctrl_stress_all.204103625 |
|
|
Mar 17 03:07:06 PM PDT 24 |
Mar 17 04:13:45 PM PDT 24 |
53710092641 ps |
| T819 |
/workspace/coverage/default/45.sram_ctrl_multiple_keys.2977913202 |
|
|
Mar 17 03:11:25 PM PDT 24 |
Mar 17 03:22:28 PM PDT 24 |
14179139462 ps |
| T820 |
/workspace/coverage/default/29.sram_ctrl_stress_all_with_rand_reset.1733841822 |
|
|
Mar 17 03:08:25 PM PDT 24 |
Mar 17 03:09:07 PM PDT 24 |
7500219760 ps |
| T821 |
/workspace/coverage/default/17.sram_ctrl_mem_walk.724882816 |
|
|
Mar 17 03:06:49 PM PDT 24 |
Mar 17 03:09:23 PM PDT 24 |
26489583653 ps |
| T822 |
/workspace/coverage/default/40.sram_ctrl_throughput_w_partial_write.1745003179 |
|
|
Mar 17 03:10:28 PM PDT 24 |
Mar 17 03:11:56 PM PDT 24 |
769740585 ps |
| T823 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.4185667536 |
|
|
Mar 17 03:06:17 PM PDT 24 |
Mar 17 03:13:43 PM PDT 24 |
81772545159 ps |
| T824 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2757223629 |
|
|
Mar 17 03:08:15 PM PDT 24 |
Mar 17 04:33:39 PM PDT 24 |
300049244445 ps |
| T825 |
/workspace/coverage/default/23.sram_ctrl_bijection.3539397255 |
|
|
Mar 17 03:07:23 PM PDT 24 |
Mar 17 03:30:30 PM PDT 24 |
240052385029 ps |
| T826 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3860761187 |
|
|
Mar 17 03:06:47 PM PDT 24 |
Mar 17 03:11:05 PM PDT 24 |
67370191853 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_alert_test.2601140721 |
|
|
Mar 17 03:11:09 PM PDT 24 |
Mar 17 03:11:10 PM PDT 24 |
109010068 ps |
| T828 |
/workspace/coverage/default/37.sram_ctrl_smoke.960319972 |
|
|
Mar 17 03:09:58 PM PDT 24 |
Mar 17 03:10:18 PM PDT 24 |
3529303473 ps |
| T829 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2367904783 |
|
|
Mar 17 03:10:35 PM PDT 24 |
Mar 17 03:23:43 PM PDT 24 |
15195710862 ps |
| T830 |
/workspace/coverage/default/1.sram_ctrl_executable.2332249805 |
|
|
Mar 17 03:05:57 PM PDT 24 |
Mar 17 03:21:14 PM PDT 24 |
15958015392 ps |
| T831 |
/workspace/coverage/default/46.sram_ctrl_mem_walk.3712182767 |
|
|
Mar 17 03:11:48 PM PDT 24 |
Mar 17 03:15:54 PM PDT 24 |
3949177780 ps |
| T832 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2543828485 |
|
|
Mar 17 03:06:03 PM PDT 24 |
Mar 17 03:07:19 PM PDT 24 |
10886006447 ps |
| T833 |
/workspace/coverage/default/27.sram_ctrl_ram_cfg.626564358 |
|
|
Mar 17 03:08:03 PM PDT 24 |
Mar 17 03:08:07 PM PDT 24 |
358643772 ps |
| T834 |
/workspace/coverage/default/10.sram_ctrl_access_during_key_req.2646248820 |
|
|
Mar 17 03:06:23 PM PDT 24 |
Mar 17 03:11:41 PM PDT 24 |
28988887417 ps |
| T835 |
/workspace/coverage/default/45.sram_ctrl_partial_access.4275921655 |
|
|
Mar 17 03:11:25 PM PDT 24 |
Mar 17 03:11:41 PM PDT 24 |
1294318541 ps |
| T836 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.218533779 |
|
|
Mar 17 03:08:09 PM PDT 24 |
Mar 17 03:12:43 PM PDT 24 |
24129147374 ps |
| T837 |
/workspace/coverage/default/21.sram_ctrl_stress_all_with_rand_reset.3164484547 |
|
|
Mar 17 03:07:18 PM PDT 24 |
Mar 17 03:08:28 PM PDT 24 |
1714349625 ps |
| T838 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.3980593272 |
|
|
Mar 17 03:11:29 PM PDT 24 |
Mar 17 03:11:51 PM PDT 24 |
7301886403 ps |
| T839 |
/workspace/coverage/default/24.sram_ctrl_regwen.400080381 |
|
|
Mar 17 03:07:32 PM PDT 24 |
Mar 17 03:22:30 PM PDT 24 |
61235163748 ps |
| T840 |
/workspace/coverage/default/29.sram_ctrl_ram_cfg.1258872994 |
|
|
Mar 17 03:08:23 PM PDT 24 |
Mar 17 03:08:26 PM PDT 24 |
349611957 ps |
| T841 |
/workspace/coverage/default/2.sram_ctrl_ram_cfg.4211680532 |
|
|
Mar 17 03:05:56 PM PDT 24 |
Mar 17 03:06:00 PM PDT 24 |
1526795851 ps |
| T842 |
/workspace/coverage/default/38.sram_ctrl_stress_all_with_rand_reset.2767908995 |
|
|
Mar 17 03:10:10 PM PDT 24 |
Mar 17 03:10:54 PM PDT 24 |
1550178136 ps |
| T843 |
/workspace/coverage/default/9.sram_ctrl_stress_all.1179400101 |
|
|
Mar 17 03:06:21 PM PDT 24 |
Mar 17 04:41:47 PM PDT 24 |
105955258628 ps |
| T844 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2871795957 |
|
|
Mar 17 03:05:58 PM PDT 24 |
Mar 17 03:06:01 PM PDT 24 |
350709717 ps |
| T845 |
/workspace/coverage/default/47.sram_ctrl_regwen.1016061861 |
|
|
Mar 17 03:12:02 PM PDT 24 |
Mar 17 03:29:22 PM PDT 24 |
15327338804 ps |
| T846 |
/workspace/coverage/default/9.sram_ctrl_multiple_keys.930485682 |
|
|
Mar 17 03:06:22 PM PDT 24 |
Mar 17 03:17:26 PM PDT 24 |
12552328235 ps |
| T847 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.1274609396 |
|
|
Mar 17 03:07:29 PM PDT 24 |
Mar 17 03:12:08 PM PDT 24 |
14361372418 ps |
| T848 |
/workspace/coverage/default/34.sram_ctrl_partial_access_b2b.1262294729 |
|
|
Mar 17 03:09:18 PM PDT 24 |
Mar 17 03:15:55 PM PDT 24 |
12681038953 ps |
| T849 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.3936150061 |
|
|
Mar 17 03:06:04 PM PDT 24 |
Mar 17 03:06:51 PM PDT 24 |
120860272405 ps |
| T850 |
/workspace/coverage/default/18.sram_ctrl_bijection.1886964304 |
|
|
Mar 17 03:06:48 PM PDT 24 |
Mar 17 03:19:51 PM PDT 24 |
51637721386 ps |
| T851 |
/workspace/coverage/default/16.sram_ctrl_alert_test.2949041536 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:06:38 PM PDT 24 |
27113612 ps |
| T852 |
/workspace/coverage/default/13.sram_ctrl_regwen.1987966057 |
|
|
Mar 17 03:06:25 PM PDT 24 |
Mar 17 03:11:51 PM PDT 24 |
3078498298 ps |
| T853 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.695347683 |
|
|
Mar 17 03:09:14 PM PDT 24 |
Mar 17 03:32:16 PM PDT 24 |
32578657391 ps |
| T854 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.109677262 |
|
|
Mar 17 03:06:38 PM PDT 24 |
Mar 17 03:06:49 PM PDT 24 |
1530807023 ps |
| T855 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.3552369920 |
|
|
Mar 17 03:07:11 PM PDT 24 |
Mar 17 03:10:34 PM PDT 24 |
9026940929 ps |
| T856 |
/workspace/coverage/default/30.sram_ctrl_access_during_key_req.2603318873 |
|
|
Mar 17 03:08:30 PM PDT 24 |
Mar 17 03:10:34 PM PDT 24 |
6585624418 ps |
| T857 |
/workspace/coverage/default/11.sram_ctrl_throughput_w_partial_write.1706945533 |
|
|
Mar 17 03:06:26 PM PDT 24 |
Mar 17 03:08:05 PM PDT 24 |
2736223302 ps |
| T858 |
/workspace/coverage/default/30.sram_ctrl_mem_partial_access.2592603102 |
|
|
Mar 17 03:08:40 PM PDT 24 |
Mar 17 03:09:53 PM PDT 24 |
2470836249 ps |
| T859 |
/workspace/coverage/default/0.sram_ctrl_max_throughput.4080736380 |
|
|
Mar 17 03:05:54 PM PDT 24 |
Mar 17 03:08:10 PM PDT 24 |
1561914580 ps |
| T860 |
/workspace/coverage/default/46.sram_ctrl_executable.1519046554 |
|
|
Mar 17 03:12:06 PM PDT 24 |
Mar 17 03:29:56 PM PDT 24 |
17212642088 ps |
| T861 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.85999239 |
|
|
Mar 17 03:06:24 PM PDT 24 |
Mar 17 03:07:32 PM PDT 24 |
77798191483 ps |
| T862 |
/workspace/coverage/default/21.sram_ctrl_regwen.2185343822 |
|
|
Mar 17 03:07:13 PM PDT 24 |
Mar 17 03:22:51 PM PDT 24 |
9948019132 ps |
| T863 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.1229026315 |
|
|
Mar 17 03:08:44 PM PDT 24 |
Mar 17 03:08:47 PM PDT 24 |
349309071 ps |
| T864 |
/workspace/coverage/default/27.sram_ctrl_max_throughput.1544934024 |
|
|
Mar 17 03:08:00 PM PDT 24 |
Mar 17 03:08:09 PM PDT 24 |
1390332362 ps |
| T865 |
/workspace/coverage/default/9.sram_ctrl_bijection.390657660 |
|
|
Mar 17 03:06:19 PM PDT 24 |
Mar 17 03:38:52 PM PDT 24 |
788634696779 ps |
| T866 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.2028996828 |
|
|
Mar 17 03:09:52 PM PDT 24 |
Mar 17 03:09:55 PM PDT 24 |
360972454 ps |
| T867 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.3014265286 |
|
|
Mar 17 03:07:19 PM PDT 24 |
Mar 17 03:09:50 PM PDT 24 |
4857876394 ps |
| T868 |
/workspace/coverage/default/16.sram_ctrl_stress_all.3174989483 |
|
|
Mar 17 03:06:36 PM PDT 24 |
Mar 17 04:40:53 PM PDT 24 |
406639867298 ps |
| T869 |
/workspace/coverage/default/24.sram_ctrl_alert_test.2586630824 |
|
|
Mar 17 03:07:43 PM PDT 24 |
Mar 17 03:07:44 PM PDT 24 |
17608197 ps |
| T870 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1541576433 |
|
|
Mar 17 03:06:30 PM PDT 24 |
Mar 17 03:06:37 PM PDT 24 |
2559529813 ps |
| T871 |
/workspace/coverage/default/31.sram_ctrl_partial_access_b2b.2879403098 |
|
|
Mar 17 03:08:45 PM PDT 24 |
Mar 17 03:12:37 PM PDT 24 |
40028552856 ps |
| T872 |
/workspace/coverage/default/42.sram_ctrl_alert_test.834685529 |
|
|
Mar 17 03:11:02 PM PDT 24 |
Mar 17 03:11:03 PM PDT 24 |
10963366 ps |
| T873 |
/workspace/coverage/default/26.sram_ctrl_multiple_keys.1812998549 |
|
|
Mar 17 03:07:51 PM PDT 24 |
Mar 17 03:10:27 PM PDT 24 |
19524582268 ps |
| T874 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.1967197767 |
|
|
Mar 17 03:06:52 PM PDT 24 |
Mar 17 03:06:56 PM PDT 24 |
710781444 ps |
| T875 |
/workspace/coverage/default/5.sram_ctrl_smoke.1070319558 |
|
|
Mar 17 03:06:08 PM PDT 24 |
Mar 17 03:06:15 PM PDT 24 |
6839329403 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_partial_access.3118816197 |
|
|
Mar 17 03:07:16 PM PDT 24 |
Mar 17 03:09:17 PM PDT 24 |
2675842361 ps |
| T877 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1807557957 |
|
|
Mar 17 03:05:58 PM PDT 24 |
Mar 17 03:06:03 PM PDT 24 |
812180954 ps |
| T878 |
/workspace/coverage/default/35.sram_ctrl_access_during_key_req.2315659127 |
|
|
Mar 17 03:09:49 PM PDT 24 |
Mar 17 03:13:22 PM PDT 24 |
10605187309 ps |
| T879 |
/workspace/coverage/default/32.sram_ctrl_executable.2795521054 |
|
|
Mar 17 03:08:56 PM PDT 24 |
Mar 17 03:12:58 PM PDT 24 |
4763403520 ps |
| T880 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3502501586 |
|
|
Mar 17 03:09:54 PM PDT 24 |
Mar 17 03:09:56 PM PDT 24 |
36856872 ps |
| T881 |
/workspace/coverage/default/29.sram_ctrl_executable.1618421288 |
|
|
Mar 17 03:08:22 PM PDT 24 |
Mar 17 03:20:38 PM PDT 24 |
6647249805 ps |
| T882 |
/workspace/coverage/default/36.sram_ctrl_bijection.2663264923 |
|
|
Mar 17 03:09:52 PM PDT 24 |
Mar 17 03:41:01 PM PDT 24 |
28163753811 ps |
| T883 |
/workspace/coverage/default/4.sram_ctrl_alert_test.3898621167 |
|
|
Mar 17 03:06:10 PM PDT 24 |
Mar 17 03:06:11 PM PDT 24 |
75889497 ps |
| T884 |
/workspace/coverage/default/30.sram_ctrl_stress_all.1286328760 |
|
|
Mar 17 03:08:41 PM PDT 24 |
Mar 17 03:22:30 PM PDT 24 |
34966835442 ps |
| T885 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.1632658013 |
|
|
Mar 17 03:11:17 PM PDT 24 |
Mar 17 03:11:47 PM PDT 24 |
4430850947 ps |
| T886 |
/workspace/coverage/default/19.sram_ctrl_mem_partial_access.1153357195 |
|
|
Mar 17 03:07:03 PM PDT 24 |
Mar 17 03:08:09 PM PDT 24 |
3953512097 ps |
| T887 |
/workspace/coverage/default/32.sram_ctrl_smoke.3670393592 |
|
|
Mar 17 03:08:49 PM PDT 24 |
Mar 17 03:08:59 PM PDT 24 |
926379105 ps |
| T888 |
/workspace/coverage/default/37.sram_ctrl_stress_pipeline.2988826130 |
|
|
Mar 17 03:10:03 PM PDT 24 |
Mar 17 03:12:20 PM PDT 24 |
23488602119 ps |
| T889 |
/workspace/coverage/default/49.sram_ctrl_throughput_w_partial_write.3898711747 |
|
|
Mar 17 03:12:22 PM PDT 24 |
Mar 17 03:12:29 PM PDT 24 |
1350984897 ps |
| T890 |
/workspace/coverage/default/9.sram_ctrl_regwen.1850239003 |
|
|
Mar 17 03:06:24 PM PDT 24 |
Mar 17 03:23:32 PM PDT 24 |
51289230113 ps |
| T891 |
/workspace/coverage/default/1.sram_ctrl_partial_access_b2b.186600799 |
|
|
Mar 17 03:06:03 PM PDT 24 |
Mar 17 03:13:08 PM PDT 24 |
258740592747 ps |
| T892 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.42985918 |
|
|
Mar 17 03:06:07 PM PDT 24 |
Mar 17 03:06:17 PM PDT 24 |
2837950269 ps |
| T893 |
/workspace/coverage/default/47.sram_ctrl_stress_all_with_rand_reset.1041266266 |
|
|
Mar 17 03:12:07 PM PDT 24 |
Mar 17 03:12:38 PM PDT 24 |
4285208583 ps |
| T894 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.1669135891 |
|
|
Mar 17 03:06:18 PM PDT 24 |
Mar 17 03:07:08 PM PDT 24 |
3044418042 ps |
| T895 |
/workspace/coverage/default/12.sram_ctrl_stress_all_with_rand_reset.2438358161 |
|
|
Mar 17 03:06:26 PM PDT 24 |
Mar 17 03:07:05 PM PDT 24 |
5578019884 ps |
| T896 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.3490970471 |
|
|
Mar 17 03:08:58 PM PDT 24 |
Mar 17 03:13:21 PM PDT 24 |
13207985450 ps |
| T897 |
/workspace/coverage/default/44.sram_ctrl_stress_all.1792486615 |
|
|
Mar 17 03:11:21 PM PDT 24 |
Mar 17 04:14:24 PM PDT 24 |
36160251136 ps |
| T898 |
/workspace/coverage/default/10.sram_ctrl_multiple_keys.1277335366 |
|
|
Mar 17 03:06:21 PM PDT 24 |
Mar 17 03:16:55 PM PDT 24 |
8620925498 ps |
| T899 |
/workspace/coverage/default/41.sram_ctrl_smoke.3917667666 |
|
|
Mar 17 03:10:39 PM PDT 24 |
Mar 17 03:10:53 PM PDT 24 |
2542635933 ps |
| T900 |
/workspace/coverage/default/29.sram_ctrl_multiple_keys.3854442422 |
|
|
Mar 17 03:08:17 PM PDT 24 |
Mar 17 03:17:46 PM PDT 24 |
10188440131 ps |
| T901 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2328496071 |
|
|
Mar 17 03:09:00 PM PDT 24 |
Mar 17 03:09:00 PM PDT 24 |
35321835 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_partial_access_b2b.2006515171 |
|
|
Mar 17 03:06:06 PM PDT 24 |
Mar 17 03:16:04 PM PDT 24 |
101790190536 ps |
| T903 |
/workspace/coverage/default/34.sram_ctrl_ram_cfg.1407680278 |
|
|
Mar 17 03:09:48 PM PDT 24 |
Mar 17 03:09:52 PM PDT 24 |
1402076884 ps |
| T904 |
/workspace/coverage/default/21.sram_ctrl_lc_escalation.2014992821 |
|
|
Mar 17 03:07:13 PM PDT 24 |
Mar 17 03:07:34 PM PDT 24 |
3181510204 ps |
| T905 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.4198136994 |
|
|
Mar 17 03:06:06 PM PDT 24 |
Mar 17 03:07:32 PM PDT 24 |
2502223403 ps |
| T906 |
/workspace/coverage/default/10.sram_ctrl_bijection.1000014756 |
|
|
Mar 17 03:06:20 PM PDT 24 |
Mar 17 03:38:47 PM PDT 24 |
29065461547 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_partial_access.914598871 |
|
|
Mar 17 03:11:56 PM PDT 24 |
Mar 17 03:12:33 PM PDT 24 |
691023949 ps |
| T908 |
/workspace/coverage/default/41.sram_ctrl_bijection.1847039940 |
|
|
Mar 17 03:10:39 PM PDT 24 |
Mar 17 03:31:38 PM PDT 24 |
211658483857 ps |
| T909 |
/workspace/coverage/default/15.sram_ctrl_executable.1965298725 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:18:54 PM PDT 24 |
10671220923 ps |
| T910 |
/workspace/coverage/default/13.sram_ctrl_partial_access_b2b.767796035 |
|
|
Mar 17 03:06:29 PM PDT 24 |
Mar 17 03:10:38 PM PDT 24 |
21944992470 ps |
| T911 |
/workspace/coverage/default/15.sram_ctrl_regwen.3786535477 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:19:17 PM PDT 24 |
47493799457 ps |
| T912 |
/workspace/coverage/default/48.sram_ctrl_partial_access.1092732841 |
|
|
Mar 17 03:12:09 PM PDT 24 |
Mar 17 03:14:01 PM PDT 24 |
1397032269 ps |
| T913 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.2231216358 |
|
|
Mar 17 03:10:27 PM PDT 24 |
Mar 17 03:20:38 PM PDT 24 |
29918111745 ps |
| T914 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2714831024 |
|
|
Mar 17 03:05:56 PM PDT 24 |
Mar 17 04:29:22 PM PDT 24 |
726526885544 ps |
| T915 |
/workspace/coverage/default/34.sram_ctrl_stress_pipeline.1539293870 |
|
|
Mar 17 03:09:14 PM PDT 24 |
Mar 17 03:15:07 PM PDT 24 |
28303877983 ps |
| T916 |
/workspace/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.3095782935 |
|
|
Mar 17 03:06:17 PM PDT 24 |
Mar 17 03:06:40 PM PDT 24 |
2455126114 ps |
| T917 |
/workspace/coverage/default/21.sram_ctrl_multiple_keys.2904181754 |
|
|
Mar 17 03:07:08 PM PDT 24 |
Mar 17 03:13:02 PM PDT 24 |
4727918142 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2443895010 |
|
|
Mar 17 03:06:20 PM PDT 24 |
Mar 17 03:06:35 PM PDT 24 |
27427641787 ps |
| T919 |
/workspace/coverage/default/29.sram_ctrl_smoke.96600136 |
|
|
Mar 17 03:08:17 PM PDT 24 |
Mar 17 03:08:54 PM PDT 24 |
1010455778 ps |
| T920 |
/workspace/coverage/default/10.sram_ctrl_executable.1147763974 |
|
|
Mar 17 03:06:24 PM PDT 24 |
Mar 17 03:34:45 PM PDT 24 |
119786291329 ps |
| T921 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.914835276 |
|
|
Mar 17 03:09:03 PM PDT 24 |
Mar 17 03:19:09 PM PDT 24 |
48266208221 ps |
| T922 |
/workspace/coverage/default/6.sram_ctrl_mem_walk.469187832 |
|
|
Mar 17 03:06:20 PM PDT 24 |
Mar 17 03:11:33 PM PDT 24 |
358088385955 ps |
| T923 |
/workspace/coverage/default/4.sram_ctrl_max_throughput.1797611713 |
|
|
Mar 17 03:06:05 PM PDT 24 |
Mar 17 03:07:28 PM PDT 24 |
1704076242 ps |
| T924 |
/workspace/coverage/default/45.sram_ctrl_stress_all.2053174787 |
|
|
Mar 17 03:11:38 PM PDT 24 |
Mar 17 03:37:22 PM PDT 24 |
29387806023 ps |
| T925 |
/workspace/coverage/default/6.sram_ctrl_alert_test.2385440741 |
|
|
Mar 17 03:06:16 PM PDT 24 |
Mar 17 03:06:16 PM PDT 24 |
24865880 ps |
| T926 |
/workspace/coverage/default/49.sram_ctrl_partial_access.1806271185 |
|
|
Mar 17 03:12:17 PM PDT 24 |
Mar 17 03:12:33 PM PDT 24 |
3342449426 ps |
| T927 |
/workspace/coverage/default/49.sram_ctrl_bijection.3217735258 |
|
|
Mar 17 03:12:22 PM PDT 24 |
Mar 17 03:44:58 PM PDT 24 |
116105909900 ps |
| T928 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.588848932 |
|
|
Mar 17 03:07:12 PM PDT 24 |
Mar 17 03:07:47 PM PDT 24 |
826628949 ps |
| T929 |
/workspace/coverage/default/32.sram_ctrl_stress_all_with_rand_reset.2912698817 |
|
|
Mar 17 03:08:59 PM PDT 24 |
Mar 17 03:09:36 PM PDT 24 |
4246653262 ps |
| T930 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1227567074 |
|
|
Mar 17 03:07:56 PM PDT 24 |
Mar 17 03:12:37 PM PDT 24 |
75216869080 ps |
| T931 |
/workspace/coverage/default/20.sram_ctrl_partial_access.2758678586 |
|
|
Mar 17 03:06:59 PM PDT 24 |
Mar 17 03:07:06 PM PDT 24 |
2785598592 ps |
| T932 |
/workspace/coverage/default/22.sram_ctrl_access_during_key_req.3538868854 |
|
|
Mar 17 03:07:16 PM PDT 24 |
Mar 17 03:26:41 PM PDT 24 |
104828410830 ps |
| T933 |
/workspace/coverage/default/31.sram_ctrl_alert_test.2918688240 |
|
|
Mar 17 03:08:47 PM PDT 24 |
Mar 17 03:08:48 PM PDT 24 |
36953117 ps |
| T934 |
/workspace/coverage/default/40.sram_ctrl_ram_cfg.3133467875 |
|
|
Mar 17 03:10:33 PM PDT 24 |
Mar 17 03:10:36 PM PDT 24 |
706821063 ps |
| T935 |
/workspace/coverage/default/26.sram_ctrl_alert_test.1255283648 |
|
|
Mar 17 03:07:55 PM PDT 24 |
Mar 17 03:07:56 PM PDT 24 |
40584520 ps |
| T936 |
/workspace/coverage/default/3.sram_ctrl_executable.4171023167 |
|
|
Mar 17 03:06:03 PM PDT 24 |
Mar 17 03:38:15 PM PDT 24 |
67951518918 ps |
| T937 |
/workspace/coverage/default/43.sram_ctrl_bijection.3229015247 |
|
|
Mar 17 03:11:03 PM PDT 24 |
Mar 17 03:53:56 PM PDT 24 |
595868066340 ps |
| T938 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.4034200103 |
|
|
Mar 17 03:06:27 PM PDT 24 |
Mar 17 03:06:30 PM PDT 24 |
600904559 ps |
| T939 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.422402299 |
|
|
Mar 17 03:11:11 PM PDT 24 |
Mar 17 03:11:48 PM PDT 24 |
3256852578 ps |
| T940 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.4135421642 |
|
|
Mar 17 03:09:55 PM PDT 24 |
Mar 17 03:10:00 PM PDT 24 |
1339337880 ps |
| T941 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.523640730 |
|
|
Mar 17 03:07:55 PM PDT 24 |
Mar 17 03:09:20 PM PDT 24 |
31153432217 ps |
| T942 |
/workspace/coverage/default/14.sram_ctrl_smoke.1486804027 |
|
|
Mar 17 03:06:37 PM PDT 24 |
Mar 17 03:06:57 PM PDT 24 |
935867325 ps |
| T943 |
/workspace/coverage/default/39.sram_ctrl_multiple_keys.813594212 |
|
|
Mar 17 03:10:17 PM PDT 24 |
Mar 17 03:32:48 PM PDT 24 |
44307787056 ps |
| T56 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3498027771 |
|
|
Mar 17 03:03:23 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
14993516 ps |
| T94 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.497594891 |
|
|
Mar 17 03:03:26 PM PDT 24 |
Mar 17 03:03:28 PM PDT 24 |
497448682 ps |
| T944 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.1000428462 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
351943203 ps |
| T95 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2066497801 |
|
|
Mar 17 03:03:15 PM PDT 24 |
Mar 17 03:03:16 PM PDT 24 |
321123035 ps |
| T91 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.3426311369 |
|
|
Mar 17 03:03:23 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
15383076 ps |
| T57 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.3897672407 |
|
|
Mar 17 03:03:18 PM PDT 24 |
Mar 17 03:04:13 PM PDT 24 |
29373265240 ps |
| T58 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1178179418 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
49418440 ps |
| T945 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.2303986411 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
1726755773 ps |
| T83 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1641141998 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:11 PM PDT 24 |
15047597 ps |
| T946 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1780207942 |
|
|
Mar 17 03:03:07 PM PDT 24 |
Mar 17 03:03:12 PM PDT 24 |
1060207940 ps |
| T947 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.4221522889 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
351957733 ps |
| T84 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.648144183 |
|
|
Mar 17 03:03:12 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
70993155 ps |
| T59 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1195271672 |
|
|
Mar 17 03:03:27 PM PDT 24 |
Mar 17 03:04:19 PM PDT 24 |
7059526523 ps |
| T948 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2397634483 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
47174536 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.3848596694 |
|
|
Mar 17 03:03:08 PM PDT 24 |
Mar 17 03:03:10 PM PDT 24 |
300476751 ps |
| T85 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1880107631 |
|
|
Mar 17 03:03:18 PM PDT 24 |
Mar 17 03:03:19 PM PDT 24 |
44058229 ps |
| T92 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.3068540550 |
|
|
Mar 17 03:03:17 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
28693148 ps |
| T93 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.963387964 |
|
|
Mar 17 03:03:05 PM PDT 24 |
Mar 17 03:03:06 PM PDT 24 |
29214025 ps |
| T950 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2329759291 |
|
|
Mar 17 03:03:23 PM PDT 24 |
Mar 17 03:03:30 PM PDT 24 |
1353160379 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.2267427500 |
|
|
Mar 17 03:03:09 PM PDT 24 |
Mar 17 03:03:12 PM PDT 24 |
256778066 ps |
| T96 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3860996138 |
|
|
Mar 17 03:03:26 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
161350223 ps |
| T60 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.2105449743 |
|
|
Mar 17 03:03:29 PM PDT 24 |
Mar 17 03:04:20 PM PDT 24 |
27089802094 ps |
| T61 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.749355322 |
|
|
Mar 17 03:03:04 PM PDT 24 |
Mar 17 03:03:55 PM PDT 24 |
31981863668 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.264863133 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:16 PM PDT 24 |
120564666 ps |
| T86 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.953306894 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:15 PM PDT 24 |
20972753 ps |
| T62 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.3143068999 |
|
|
Mar 17 03:03:17 PM PDT 24 |
Mar 17 03:04:11 PM PDT 24 |
29438544341 ps |
| T953 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1930973894 |
|
|
Mar 17 03:03:26 PM PDT 24 |
Mar 17 03:03:31 PM PDT 24 |
729322472 ps |
| T954 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3976978425 |
|
|
Mar 17 03:03:12 PM PDT 24 |
Mar 17 03:03:14 PM PDT 24 |
15639854 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.3022538236 |
|
|
Mar 17 03:03:12 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
38409620 ps |
| T956 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.765592562 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:17 PM PDT 24 |
14158564 ps |
| T106 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.2054982418 |
|
|
Mar 17 03:03:17 PM PDT 24 |
Mar 17 03:03:19 PM PDT 24 |
118023735 ps |
| T957 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2478132555 |
|
|
Mar 17 03:03:30 PM PDT 24 |
Mar 17 03:03:34 PM PDT 24 |
62682235 ps |
| T103 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.2458332352 |
|
|
Mar 17 03:03:30 PM PDT 24 |
Mar 17 03:03:33 PM PDT 24 |
1250763636 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.316127233 |
|
|
Mar 17 03:03:15 PM PDT 24 |
Mar 17 03:03:16 PM PDT 24 |
11410535 ps |
| T958 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1212309538 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:20 PM PDT 24 |
226930653 ps |
| T64 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.3118225071 |
|
|
Mar 17 03:03:18 PM PDT 24 |
Mar 17 03:03:20 PM PDT 24 |
20621163 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.1260588096 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:20 PM PDT 24 |
358407821 ps |
| T960 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.2836884110 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:16 PM PDT 24 |
66076115 ps |
| T961 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.1150777984 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:11 PM PDT 24 |
63863241 ps |
| T65 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.1381596808 |
|
|
Mar 17 03:03:17 PM PDT 24 |
Mar 17 03:03:44 PM PDT 24 |
14755026773 ps |
| T962 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2526100880 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:14 PM PDT 24 |
713953072 ps |
| T67 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.3191961323 |
|
|
Mar 17 03:03:25 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
17664115 ps |
| T104 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.242439066 |
|
|
Mar 17 03:03:12 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
221606328 ps |
| T963 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1849094306 |
|
|
Mar 17 03:03:11 PM PDT 24 |
Mar 17 03:03:16 PM PDT 24 |
3472309095 ps |
| T110 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1703962411 |
|
|
Mar 17 03:03:18 PM PDT 24 |
Mar 17 03:03:20 PM PDT 24 |
1467648702 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.1481138207 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:15 PM PDT 24 |
44844914 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.4176077316 |
|
|
Mar 17 03:03:11 PM PDT 24 |
Mar 17 03:04:03 PM PDT 24 |
29393629981 ps |
| T966 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1211217746 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
111416195 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3374012892 |
|
|
Mar 17 03:03:08 PM PDT 24 |
Mar 17 03:03:09 PM PDT 24 |
51475739 ps |
| T968 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.623364177 |
|
|
Mar 17 03:03:21 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
95440515 ps |
| T969 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.461989358 |
|
|
Mar 17 03:03:28 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
31167974 ps |
| T970 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1132513381 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:04:13 PM PDT 24 |
14833048957 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2542728465 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
139483687 ps |
| T74 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.503986672 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:04:02 PM PDT 24 |
7285532705 ps |
| T112 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.154123289 |
|
|
Mar 17 03:03:29 PM PDT 24 |
Mar 17 03:03:31 PM PDT 24 |
136884636 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2530451632 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:12 PM PDT 24 |
279975081 ps |
| T108 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2568058352 |
|
|
Mar 17 03:03:21 PM PDT 24 |
Mar 17 03:03:28 PM PDT 24 |
770257976 ps |
| T113 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.2582624664 |
|
|
Mar 17 03:03:15 PM PDT 24 |
Mar 17 03:03:17 PM PDT 24 |
754605725 ps |
| T971 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2053718404 |
|
|
Mar 17 03:03:20 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
247269078 ps |
| T972 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3135490227 |
|
|
Mar 17 03:03:13 PM PDT 24 |
Mar 17 03:03:14 PM PDT 24 |
42325303 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.358600256 |
|
|
Mar 17 03:03:25 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
72099242 ps |
| T75 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.1898015198 |
|
|
Mar 17 03:03:20 PM PDT 24 |
Mar 17 03:03:26 PM PDT 24 |
98985288 ps |
| T974 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.2587049171 |
|
|
Mar 17 03:03:21 PM PDT 24 |
Mar 17 03:03:32 PM PDT 24 |
160788038 ps |
| T975 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.872615938 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:20 PM PDT 24 |
455543787 ps |
| T976 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.3079863531 |
|
|
Mar 17 03:03:08 PM PDT 24 |
Mar 17 03:03:10 PM PDT 24 |
378990448 ps |
| T977 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3255963278 |
|
|
Mar 17 03:03:20 PM PDT 24 |
Mar 17 03:04:00 PM PDT 24 |
21732234352 ps |
| T978 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3722601722 |
|
|
Mar 17 03:03:14 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
122949375 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.2090895528 |
|
|
Mar 17 03:03:11 PM PDT 24 |
Mar 17 03:03:17 PM PDT 24 |
369497688 ps |
| T980 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.395197659 |
|
|
Mar 17 03:03:28 PM PDT 24 |
Mar 17 03:03:32 PM PDT 24 |
354910114 ps |
| T79 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.1912062575 |
|
|
Mar 17 03:03:09 PM PDT 24 |
Mar 17 03:03:11 PM PDT 24 |
24944029 ps |
| T981 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.532378679 |
|
|
Mar 17 03:03:23 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
25429153 ps |
| T982 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2366514305 |
|
|
Mar 17 03:03:15 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
135572520 ps |
| T983 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2021906225 |
|
|
Mar 17 03:03:27 PM PDT 24 |
Mar 17 03:03:33 PM PDT 24 |
362487444 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.4030944333 |
|
|
Mar 17 03:03:12 PM PDT 24 |
Mar 17 03:03:12 PM PDT 24 |
33042461 ps |
| T985 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2842868787 |
|
|
Mar 17 03:03:21 PM PDT 24 |
Mar 17 03:03:55 PM PDT 24 |
17577421565 ps |
| T105 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1861414954 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:13 PM PDT 24 |
471756139 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3848773344 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:14 PM PDT 24 |
371349581 ps |
| T987 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.178291799 |
|
|
Mar 17 03:03:24 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
73302976 ps |
| T76 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.3800290913 |
|
|
Mar 17 03:03:08 PM PDT 24 |
Mar 17 03:03:09 PM PDT 24 |
53803691 ps |
| T988 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3446916548 |
|
|
Mar 17 03:03:25 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
27608822 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.3040502454 |
|
|
Mar 17 03:03:17 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
15332499 ps |
| T990 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2968274597 |
|
|
Mar 17 03:03:27 PM PDT 24 |
Mar 17 03:03:28 PM PDT 24 |
73091387 ps |
| T991 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3876433279 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:12 PM PDT 24 |
328866363 ps |
| T992 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.3266560593 |
|
|
Mar 17 03:03:06 PM PDT 24 |
Mar 17 03:03:34 PM PDT 24 |
3728252394 ps |
| T77 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.65253012 |
|
|
Mar 17 03:03:25 PM PDT 24 |
Mar 17 03:04:15 PM PDT 24 |
8909441666 ps |
| T107 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2193252556 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
76621712 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1609882713 |
|
|
Mar 17 03:03:20 PM PDT 24 |
Mar 17 03:03:26 PM PDT 24 |
89205249 ps |
| T994 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.339435688 |
|
|
Mar 17 03:03:25 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
21634246 ps |
| T78 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1809103141 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:04:05 PM PDT 24 |
43968318480 ps |
| T995 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.811452082 |
|
|
Mar 17 03:03:13 PM PDT 24 |
Mar 17 03:03:18 PM PDT 24 |
1459233028 ps |
| T115 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.626827313 |
|
|
Mar 17 03:03:26 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
578478931 ps |
| T80 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.455003872 |
|
|
Mar 17 03:03:26 PM PDT 24 |
Mar 17 03:04:24 PM PDT 24 |
24280880722 ps |
| T996 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4272716936 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:29 PM PDT 24 |
190445175 ps |
| T997 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.3422405881 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:30 PM PDT 24 |
2154551309 ps |
| T998 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3851518416 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
19222929 ps |
| T999 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3289991264 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
46691028 ps |
| T81 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.563764170 |
|
|
Mar 17 03:03:20 PM PDT 24 |
Mar 17 03:03:26 PM PDT 24 |
34151282 ps |
| T1000 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1494698502 |
|
|
Mar 17 03:03:16 PM PDT 24 |
Mar 17 03:03:17 PM PDT 24 |
14257611 ps |
| T1001 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1394264722 |
|
|
Mar 17 03:03:22 PM PDT 24 |
Mar 17 03:03:27 PM PDT 24 |
29502477 ps |
| T1002 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.1115405377 |
|
|
Mar 17 03:03:10 PM PDT 24 |
Mar 17 03:03:14 PM PDT 24 |
1738622953 ps |