Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16069021	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

165081958

1

T1

36384

T2

193036

T3

142722

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	89265089	1			T1	99726		T2	106272		T3	78619
values[0x0]	44339937	1			T1	33959		T2	51070		T3	37568
values[0x1]	47545953	1			T1	66752		T2	54985		T3	40756

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8171236	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

172979743

1

T1

118949

T2

202735

T3

149841

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	642296	1			T1	811		T2	802		T3	604
valid_sources[0x01]	682419	1			T1	799		T2	805		T3	645
valid_sources[0x02]	584674	1			T1	823		T2	735		T3	595
valid_sources[0x03]	605107	1			T1	652		T2	763		T3	545
valid_sources[0x04]	587863	1			T1	679		T2	874		T3	676
valid_sources[0x05]	620879	1			T1	785		T2	747		T3	649
valid_sources[0x06]	600420	1			T1	769		T2	810		T3	624
valid_sources[0x07]	618321	1			T1	677		T2	873		T3	635
valid_sources[0x08]	586806	1			T1	832		T2	849		T3	658
valid_sources[0x09]	595673	1			T1	976		T2	730		T3	615
valid_sources[0x0a]	582517	1			T1	802		T2	718		T3	685
valid_sources[0x0b]	1900040	1			T1	718		T2	756		T3	606
valid_sources[0x0c]	615745	1			T1	668		T2	819		T3	609
valid_sources[0x0d]	599498	1			T1	656		T2	814		T3	643
valid_sources[0x0e]	592983	1			T1	828		T2	872		T3	583
valid_sources[0x0f]	611655	1			T1	787		T2	843		T3	550
valid_sources[0x10]	671474	1			T1	599		T2	816		T3	662
valid_sources[0x11]	625286	1			T1	628		T2	833		T3	699
valid_sources[0x12]	603935	1			T1	801		T2	1019		T3	601
valid_sources[0x13]	593056	1			T1	737		T2	849		T3	586
valid_sources[0x14]	623868	1			T1	690		T2	838		T3	617
valid_sources[0x15]	626144	1			T1	794		T2	811		T3	585
valid_sources[0x16]	607444	1			T1	890		T2	780		T3	613
valid_sources[0x17]	601162	1			T1	704		T2	864		T3	616
valid_sources[0x18]	594020	1			T1	853		T2	865		T3	649
valid_sources[0x19]	629282	1			T1	767		T2	791		T3	611
valid_sources[0x1a]	595178	1			T1	806		T2	817		T3	684
valid_sources[0x1b]	599830	1			T1	804		T2	751		T3	521
valid_sources[0x1c]	608206	1			T1	795		T2	851		T3	550
valid_sources[0x1d]	624255	1			T1	777		T2	816		T3	620
valid_sources[0x1e]	638160	1			T1	884		T2	777		T3	622
valid_sources[0x1f]	578671	1			T1	666		T2	875		T3	624
valid_sources[0x20]	582405	1			T1	808		T2	862		T3	664
valid_sources[0x21]	592345	1			T1	708		T2	792		T3	599
valid_sources[0x22]	584087	1			T1	830		T2	909		T3	586
valid_sources[0x23]	696009	1			T1	891		T2	765		T3	610
valid_sources[0x24]	620335	1			T1	716		T2	825		T3	608
valid_sources[0x25]	616731	1			T1	727		T2	745		T3	551
valid_sources[0x26]	622074	1			T1	792		T2	796		T3	634
valid_sources[0x27]	733692	1			T1	872		T2	897		T3	613
valid_sources[0x28]	604874	1			T1	895		T2	851		T3	562
valid_sources[0x29]	683647	1			T1	850		T2	778		T3	629
valid_sources[0x2a]	614495	1			T1	834		T2	771		T3	616
valid_sources[0x2b]	639170	1			T1	809		T2	778		T3	614
valid_sources[0x2c]	639085	1			T1	803		T2	809		T3	598
valid_sources[0x2d]	615909	1			T1	844		T2	853		T3	649
valid_sources[0x2e]	649966	1			T1	768		T2	870		T3	598
valid_sources[0x2f]	582332	1			T1	775		T2	752		T3	616
valid_sources[0x30]	632846	1			T1	854		T2	982		T3	675
valid_sources[0x31]	592927	1			T1	654		T2	864		T3	615
valid_sources[0x32]	655398	1			T1	879		T2	799		T3	546
valid_sources[0x33]	1081588	1			T1	789		T2	841		T3	607
valid_sources[0x34]	599931	1			T1	772		T2	863		T3	580
valid_sources[0x35]	633538	1			T1	920		T2	877		T3	579
valid_sources[0x36]	648706	1			T1	808		T2	759		T3	643
valid_sources[0x37]	637389	1			T1	804		T2	779		T3	583
valid_sources[0x38]	680133	1			T1	796		T2	934		T3	535
valid_sources[0x39]	592999	1			T1	894		T2	732		T3	600
valid_sources[0x3a]	699124	1			T1	768		T2	852		T3	606
valid_sources[0x3b]	628238	1			T1	878		T2	846		T3	653
valid_sources[0x3c]	600984	1			T1	729		T2	833		T3	554
valid_sources[0x3d]	640860	1			T1	861		T2	736		T3	612
valid_sources[0x3e]	617970	1			T1	780		T2	812		T3	642
valid_sources[0x3f]	601176	1			T1	813		T2	883		T3	588
valid_sources[0x40]	593285	1			T1	788		T2	914		T3	599
valid_sources[0x41]	635752	1			T1	773		T2	784		T3	635
valid_sources[0x42]	645438	1			T1	737		T2	808		T3	642
valid_sources[0x43]	592856	1			T1	744		T2	770		T3	609
valid_sources[0x44]	609048	1			T1	796		T2	775		T3	633
valid_sources[0x45]	613492	1			T1	866		T2	893		T3	660
valid_sources[0x46]	612320	1			T1	848		T2	903		T3	617
valid_sources[0x47]	648051	1			T1	693		T2	793		T3	610
valid_sources[0x48]	585109	1			T1	751		T2	823		T3	623
valid_sources[0x49]	619048	1			T1	737		T2	811		T3	603
valid_sources[0x4a]	601982	1			T1	711		T2	855		T3	570
valid_sources[0x4b]	590485	1			T1	747		T2	734		T3	564
valid_sources[0x4c]	629021	1			T1	697		T2	915		T3	648
valid_sources[0x4d]	646757	1			T1	759		T2	800		T3	551
valid_sources[0x4e]	704637	1			T1	872		T2	819		T3	555
valid_sources[0x4f]	618828	1			T1	703		T2	860		T3	617
valid_sources[0x50]	598593	1			T1	796		T2	719		T3	586
valid_sources[0x51]	588073	1			T1	786		T2	876		T3	628
valid_sources[0x52]	608325	1			T1	883		T2	818		T3	554
valid_sources[0x53]	595482	1			T1	864		T2	813		T3	599
valid_sources[0x54]	630653	1			T1	623		T2	753		T3	666
valid_sources[0x55]	662182	1			T1	877		T2	827		T3	584
valid_sources[0x56]	706262	1			T1	922		T2	729		T3	662
valid_sources[0x57]	592393	1			T1	786		T2	833		T3	577
valid_sources[0x58]	596374	1			T1	834		T2	779		T3	667
valid_sources[0x59]	598590	1			T1	869		T2	801		T3	625
valid_sources[0x5a]	600087	1			T1	721		T2	733		T3	677
valid_sources[0x5b]	673667	1			T1	730		T2	945		T3	551
valid_sources[0x5c]	596809	1			T1	762		T2	699		T3	557
valid_sources[0x5d]	601924	1			T1	727		T2	837		T3	707
valid_sources[0x5e]	599038	1			T1	942		T2	771		T3	661
valid_sources[0x5f]	616671	1			T1	814		T2	929		T3	634
valid_sources[0x60]	683420	1			T1	781		T2	840		T3	611
valid_sources[0x61]	583514	1			T1	715		T2	786		T3	554
valid_sources[0x62]	592672	1			T1	851		T2	792		T3	617
valid_sources[0x63]	672500	1			T1	882		T2	870		T3	642
valid_sources[0x64]	603260	1			T1	862		T2	828		T3	601
valid_sources[0x65]	589928	1			T1	871		T2	985		T3	590
valid_sources[0x66]	619336	1			T1	757		T2	985		T3	548
valid_sources[0x67]	640271	1			T1	677		T2	872		T3	584
valid_sources[0x68]	607441	1			T1	648		T2	861		T3	615
valid_sources[0x69]	684059	1			T1	878		T2	907		T3	642
valid_sources[0x6a]	675075	1			T1	830		T2	759		T3	620
valid_sources[0x6b]	709715	1			T1	746		T2	740		T3	540
valid_sources[0x6c]	2061806	1			T1	754		T2	952		T3	625
valid_sources[0x6d]	615026	1			T1	695		T2	840		T3	640
valid_sources[0x6e]	674215	1			T1	867		T2	873		T3	566
valid_sources[0x6f]	590828	1			T1	663		T2	869		T3	580
valid_sources[0x70]	578540	1			T1	734		T2	928		T3	634
valid_sources[0x71]	609864	1			T1	834		T2	837		T3	578
valid_sources[0x72]	689557	1			T1	765		T2	879		T3	596
valid_sources[0x73]	657127	1			T1	797		T2	812		T3	669
valid_sources[0x74]	588619	1			T1	744		T2	890		T3	647
valid_sources[0x75]	623309	1			T1	745		T2	925		T3	634
valid_sources[0x76]	624499	1			T1	729		T2	798		T3	673
valid_sources[0x77]	586310	1			T1	727		T2	738		T3	620
valid_sources[0x78]	622887	1			T1	819		T2	808		T3	647
valid_sources[0x79]	588006	1			T1	774		T2	783		T3	609
valid_sources[0x7a]	607682	1			T1	718		T2	857		T3	604
valid_sources[0x7b]	592718	1			T1	783		T2	827		T3	620
valid_sources[0x7c]	604172	1			T1	703		T2	846		T3	611
valid_sources[0x7d]	676208	1			T1	743		T2	958		T3	612
valid_sources[0x7e]	723702	1			T1	760		T2	823		T3	615
valid_sources[0x7f]	591714	1			T1	683		T2	727		T3	589
valid_sources[0x80]	703022	1			T1	755		T2	722		T3	572

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

81190610

1

T1

18252

T2

96578

T3

71596

values[0x0]

all_enables

biggest_size

41941769

1

T1

9157

T2

48187

T3

35438

values[0x1]

all_enables

biggest_size

41949579

1

T1

8975

T2

48271

T3

35688

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34135	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156549

1

T1

2

T3

2

T9

2952

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54941	1			T9	851		T6	33		T7	31
values[0x0]	65838	1			T1	4		T2	5		T3	2
values[0x1]	69905	1			T1	2		T2	1		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25745	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164939

1

T1

3

T3

2

T9

3064

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	974	1			T9	20		T69	2		T72	1
valid_sources[0x01]	1257	1			T9	8		T62	1		T25	13
valid_sources[0x02]	804	1			T9	17		T24	1		T40	1
valid_sources[0x03]	659	1			T9	16		T7	1		T132	1
valid_sources[0x04]	657	1			T9	11		T132	1		T24	2
valid_sources[0x05]	774	1			T9	10		T13	1		T61	1
valid_sources[0x06]	918	1			T9	10		T7	4		T5	5
valid_sources[0x07]	630	1			T9	14		T49	1		T25	4
valid_sources[0x08]	590	1			T9	15		T13	2		T25	3
valid_sources[0x09]	656	1			T9	6		T24	3		T25	6
valid_sources[0x0a]	709	1			T9	12		T25	2		T133	2
valid_sources[0x0b]	931	1			T9	23		T7	1		T12	1
valid_sources[0x0c]	690	1			T9	20		T25	9		T26	15
valid_sources[0x0d]	741	1			T9	7		T72	1		T40	1
valid_sources[0x0e]	727	1			T9	7		T12	2		T13	1
valid_sources[0x0f]	783	1			T9	16		T5	1		T132	1
valid_sources[0x10]	662	1			T9	20		T7	1		T63	1
valid_sources[0x11]	602	1			T9	12		T8	1		T63	1
valid_sources[0x12]	758	1			T9	8		T49	3		T25	7
valid_sources[0x13]	836	1			T9	10		T5	4		T22	188
valid_sources[0x14]	665	1			T9	11		T49	1		T25	7
valid_sources[0x15]	685	1			T9	14		T5	1		T12	1
valid_sources[0x16]	856	1			T9	14		T5	2		T13	2
valid_sources[0x17]	764	1			T9	12		T69	1		T24	3
valid_sources[0x18]	607	1			T9	8		T5	2		T50	1
valid_sources[0x19]	870	1			T9	10		T7	1		T74	1
valid_sources[0x1a]	781	1			T9	8		T5	1		T12	1
valid_sources[0x1b]	599	1			T9	13		T13	1		T40	1
valid_sources[0x1c]	624	1			T9	7		T7	1		T8	2
valid_sources[0x1d]	682	1			T9	17		T24	3		T74	1
valid_sources[0x1e]	665	1			T9	12		T62	1		T63	2
valid_sources[0x1f]	789	1			T9	9		T6	6		T25	9
valid_sources[0x20]	590	1			T9	13		T63	1		T24	1
valid_sources[0x21]	932	1			T9	12		T5	8		T63	1
valid_sources[0x22]	736	1			T9	17		T5	3		T49	2
valid_sources[0x23]	884	1			T9	15		T49	1		T50	2
valid_sources[0x24]	579	1			T9	12		T7	1		T25	6
valid_sources[0x25]	603	1			T9	12		T24	1		T49	1
valid_sources[0x26]	612	1			T9	8		T62	1		T63	1
valid_sources[0x27]	754	1			T9	10		T14	3		T132	1
valid_sources[0x28]	678	1			T9	15		T24	1		T50	1
valid_sources[0x29]	596	1			T9	9		T6	6		T24	1
valid_sources[0x2a]	610	1			T9	11		T5	6		T74	1
valid_sources[0x2b]	653	1			T9	16		T69	1		T24	1
valid_sources[0x2c]	645	1			T9	16		T7	4		T13	1
valid_sources[0x2d]	537	1			T9	7		T72	1		T49	3
valid_sources[0x2e]	832	1			T9	13		T50	6		T18	1
valid_sources[0x2f]	767	1			T9	22		T7	1		T5	1
valid_sources[0x30]	847	1			T9	14		T8	3		T13	1
valid_sources[0x31]	688	1			T9	10		T17	9		T50	2
valid_sources[0x32]	623	1			T9	10		T11	2		T74	1
valid_sources[0x33]	715	1			T9	17		T13	2		T50	1
valid_sources[0x34]	672	1			T3	1		T9	11		T72	1
valid_sources[0x35]	719	1			T9	21		T4	1		T24	1
valid_sources[0x36]	654	1			T9	15		T63	1		T24	1
valid_sources[0x37]	866	1			T9	15		T7	3		T50	1
valid_sources[0x38]	770	1			T9	15		T5	1		T12	2
valid_sources[0x39]	624	1			T9	15		T50	1		T126	1
valid_sources[0x3a]	721	1			T9	13		T69	1		T24	3
valid_sources[0x3b]	909	1			T9	11		T24	2		T74	1
valid_sources[0x3c]	752	1			T9	7		T63	1		T24	3
valid_sources[0x3d]	658	1			T9	15		T62	1		T24	2
valid_sources[0x3e]	641	1			T9	8		T62	1		T63	1
valid_sources[0x3f]	730	1			T9	12		T5	6		T24	1
valid_sources[0x40]	689	1			T9	9		T13	1		T24	1
valid_sources[0x41]	677	1			T9	17		T62	1		T63	1
valid_sources[0x42]	689	1			T9	11		T12	3		T132	2
valid_sources[0x43]	634	1			T9	16		T7	2		T40	1
valid_sources[0x44]	977	1			T9	8		T40	1		T50	3
valid_sources[0x45]	1126	1			T9	10		T24	1		T50	1
valid_sources[0x46]	861	1			T9	12		T25	10		T134	1
valid_sources[0x47]	736	1			T9	10		T62	1		T69	5
valid_sources[0x48]	692	1			T9	15		T74	1		T49	1
valid_sources[0x49]	620	1			T9	12		T24	1		T25	4
valid_sources[0x4a]	631	1			T9	4		T5	2		T50	1
valid_sources[0x4b]	852	1			T9	9		T7	1		T63	1
valid_sources[0x4c]	832	1			T9	8		T126	1		T25	3
valid_sources[0x4d]	741	1			T9	12		T24	3		T25	3
valid_sources[0x4e]	1028	1			T9	9		T8	2		T25	6
valid_sources[0x4f]	750	1			T9	15		T8	1		T14	2
valid_sources[0x50]	757	1			T9	8		T5	1		T25	9
valid_sources[0x51]	619	1			T9	10		T132	1		T25	5
valid_sources[0x52]	569	1			T9	21		T24	1		T40	1
valid_sources[0x53]	868	1			T9	10		T24	4		T74	1
valid_sources[0x54]	854	1			T9	7		T49	1		T25	9
valid_sources[0x55]	640	1			T9	15		T69	1		T49	1
valid_sources[0x56]	884	1			T9	15		T12	1		T63	1
valid_sources[0x57]	652	1			T9	12		T13	3		T63	1
valid_sources[0x58]	986	1			T9	14		T24	1		T49	1
valid_sources[0x59]	780	1			T9	12		T72	1		T24	3
valid_sources[0x5a]	726	1			T9	13		T13	3		T14	3
valid_sources[0x5b]	961	1			T9	13		T7	5		T132	1
valid_sources[0x5c]	627	1			T9	12		T12	1		T40	3
valid_sources[0x5d]	782	1			T9	9		T13	3		T69	2
valid_sources[0x5e]	651	1			T3	2		T9	9		T5	2
valid_sources[0x5f]	863	1			T9	8		T132	1		T24	1
valid_sources[0x60]	857	1			T9	11		T12	1		T24	3
valid_sources[0x61]	772	1			T9	11		T25	7		T112	2
valid_sources[0x62]	730	1			T9	14		T13	2		T74	1
valid_sources[0x63]	882	1			T9	13		T5	3		T25	6
valid_sources[0x64]	657	1			T9	5		T40	1		T25	10
valid_sources[0x65]	736	1			T9	8		T5	1		T24	1
valid_sources[0x66]	669	1			T3	1		T9	10		T7	4
valid_sources[0x67]	846	1			T9	8		T48	1		T49	4
valid_sources[0x68]	742	1			T9	15		T62	1		T24	1
valid_sources[0x69]	695	1			T9	8		T24	1		T49	2
valid_sources[0x6a]	734	1			T9	8		T7	4		T12	1
valid_sources[0x6b]	847	1			T9	9		T69	2		T74	1
valid_sources[0x6c]	816	1			T9	18		T28	1		T24	1
valid_sources[0x6d]	718	1			T9	15		T5	2		T49	3
valid_sources[0x6e]	734	1			T9	11		T7	1		T13	2
valid_sources[0x6f]	746	1			T9	10		T132	1		T135	2
valid_sources[0x70]	925	1			T9	13		T50	2		T25	4
valid_sources[0x71]	688	1			T9	5		T49	2		T25	6
valid_sources[0x72]	648	1			T9	11		T7	1		T25	12
valid_sources[0x73]	698	1			T9	10		T24	2		T74	1
valid_sources[0x74]	974	1			T9	18		T25	4		T26	17
valid_sources[0x75]	646	1			T9	17		T13	1		T24	1
valid_sources[0x76]	698	1			T9	5		T49	1		T25	3
valid_sources[0x77]	651	1			T9	16		T12	1		T8	1
valid_sources[0x78]	679	1			T9	11		T5	2		T71	1
valid_sources[0x79]	822	1			T9	17		T16	15		T69	3
valid_sources[0x7a]	614	1			T9	19		T7	1		T63	1
valid_sources[0x7b]	756	1			T9	11		T8	4		T40	1
valid_sources[0x7c]	672	1			T9	11		T74	1		T25	7
valid_sources[0x7d]	639	1			T9	15		T25	7		T125	1
valid_sources[0x7e]	739	1			T9	6		T7	1		T50	1
valid_sources[0x7f]	638	1			T9	10		T62	1		T49	1
valid_sources[0x80]	573	1			T9	8		T62	1		T24	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42541

1

T9

778

T6

15

T7

21

values[0x0]

all_enables

biggest_size

57906

1

T1

1

T3

1

T9

1077

values[0x1]

all_enables

biggest_size

56102

1

T1

1

T3

1

T9

1097