Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15984759

1

T1

164053

T2

19291

T3

14221

full_word

161975054

1

T1

36384

T2

193036

T3

142722

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	177959493	1			T1	200437		T2	212327		T3	156943
auto[TlIntgErrCmd]	109	1			T101	5		T102	9		T103	9
auto[TlIntgErrData]	106	1			T101	7		T102	5		T103	4
auto[TlIntgErrBoth]	105	1			T101	8		T102	6		T103	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85974916

1

T1

99726

T2

106272

T3

78619

auto[1]

91984897

1

T1

100711

T2

106055

T3

78324

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7816474	1			T1	81474		T2	9694		T3	7023
auto[TlIntgErrNone]	partial	auto[1]	8167984	1			T1	82579		T2	9597		T3	7198
auto[TlIntgErrNone]	full_word	auto[0]	78158291	1			T1	18252		T2	96578		T3	71596
auto[TlIntgErrNone]	full_word	auto[1]	83816744	1			T1	18132		T2	96458		T3	71126
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T102	3		T103	3		T113	4
auto[TlIntgErrCmd]	partial	auto[1]	53	1			T101	4		T102	6		T103	5
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T103	1		T119	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T101	1		T121	1		-	-
auto[TlIntgErrData]	partial	auto[0]	57	1			T101	6		T102	5		T103	2
auto[TlIntgErrData]	partial	auto[1]	43	1			T101	1		T103	1		T113	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T103	1		T122	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T113	1		T115	1		T118	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T101	2		T102	1		T103	4
auto[TlIntgErrBoth]	partial	auto[1]	62	1			T101	4		T102	4		T103	3
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T101	1		T115	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1			T101	1		T102	1		T113	1