Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	937343	1			T1	22882		T5	1584		T11	1111
auto[1]	10850079	1			T1	19902		T2	88481		T3	65383
auto[2]	735629	1			T1	16574		T5	665		T11	1007
auto[3]	10603244	1			T1	13594		T2	88291		T3	65226

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14857422	1			T1	1713		T2	147483		T3	108834
auto[1]	2069649	1			T1	10484		T2	13906		T3	10508
auto[2]	2108055	1			T1	8690		T2	14056		T3	10310
auto[3]	4091169	1			T1	52065		T2	1327		T3	957

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10829751

1

T1

13

T2

46

T3

36

auto[1]

12296544

1

T1

72939

T2

176726

T3

130573

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	408142	1			T5	1310		T11	23		T22	6566
auto[0]	auto[0]	auto[1]	42265	1			T5	120		T11	179		T22	660
auto[0]	auto[0]	auto[2]	42363	1			T5	142		T11	166		T22	647
auto[0]	auto[0]	auto[3]	110600	1			T1	4		T5	12		T11	743
auto[0]	auto[1]	auto[0]	3550079	1			T2	22		T3	20		T6	500
auto[0]	auto[1]	auto[1]	379104	1			T1	1		T6	43		T7	40
auto[0]	auto[1]	auto[2]	408495	1			T2	1		T6	41		T7	44
auto[0]	auto[1]	auto[3]	643237	1			T1	4		T6	4		T7	3
auto[0]	auto[2]	auto[0]	313356	1			T5	532		T11	41		T8	1
auto[0]	auto[2]	auto[1]	40381	1			T5	48		T11	178		T22	426
auto[0]	auto[2]	auto[2]	30048	1			T5	75		T11	149		T8	1
auto[0]	auto[2]	auto[3]	75880	1			T1	4		T5	10		T11	639
auto[0]	auto[3]	auto[0]	3409320	1			T2	23		T3	14		T6	491
auto[0]	auto[3]	auto[1]	389501	1			T3	1		T6	48		T7	40
auto[0]	auto[3]	auto[2]	408387	1			T3	1		T6	40		T7	36
auto[0]	auto[3]	auto[3]	578593	1			T6	2		T7	2		T5	15
auto[1]	auto[0]	auto[0]	11254	1			T1	814		T22	1		T49	2
auto[1]	auto[0]	auto[1]	49685	1			T1	3479		T99	4375		T129	2099
auto[1]	auto[0]	auto[2]	49682	1			T1	3408		T99	4410		T130	1
auto[1]	auto[0]	auto[3]	223352	1			T1	15177		T88	3		T99	19473
auto[1]	auto[1]	auto[0]	3577885	1			T1	131		T2	73728		T3	54468
auto[1]	auto[1]	auto[1]	585307	1			T1	3487		T2	6606		T3	5033
auto[1]	auto[1]	auto[2]	551430	1			T1	573		T2	7455		T3	5396
auto[1]	auto[1]	auto[3]	1154542	1			T1	15706		T2	669		T3	466
auto[1]	auto[2]	auto[0]	8627	1			T1	688		T49	2		T131	1
auto[1]	auto[2]	auto[1]	40165	1			T1	3213		T99	4068		T129	1262
auto[1]	auto[2]	auto[2]	41306	1			T1	2285		T49	1		T99	2998
auto[1]	auto[2]	auto[3]	185866	1			T1	10384		T99	13009		T129	8935
auto[1]	auto[3]	auto[0]	3578759	1			T1	80		T2	73710		T3	54332
auto[1]	auto[3]	auto[1]	543241	1			T1	304		T2	7300		T3	5474
auto[1]	auto[3]	auto[2]	576344	1			T1	2424		T2	6600		T3	4913
auto[1]	auto[3]	auto[3]	1119099	1			T1	10786		T2	658		T3	491