Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1168273587	149967	0	0
ctrl_regwen_rd_A	1168273587	10577	0	0
exec_rd_A	1168273587	9691	0	0
exec_regwen_rd_A	1168273587	10720	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168273587	149967	0	0
T4	68865	0	0	0
T5	109345	0	0	0
T6	110319	0	0	0
T7	868384	0	0	0
T8	774358	0	0	0
T9	59205	3137	0	0
T10	33639	0	0	0
T11	120716	0	0	0
T12	165013	0	0	0
T25	0	1753	0	0
T26	0	3579	0	0
T41	0	1087	0	0
T42	0	1966	0	0
T43	0	1204	0	0
T44	0	796	0	0
T45	0	825	0	0
T46	0	1413	0	0
T47	0	4854	0	0
T48	230055	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168273587	10577	0	0
T19	33933	0	0	0
T31	246312	0	0	0
T32	465207	0	0	0
T33	240707	0	0	0
T34	34113	0	0	0
T35	1449	0	0	0
T36	1011	0	0	0
T37	44216	0	0	0
T38	234093	0	0	0
T44	28919	91	0	0
T45	0	332	0	0
T46	0	402	0	0
T104	0	958	0	0
T105	0	347	0	0
T106	0	292	0	0
T107	0	705	0	0
T108	0	513	0	0
T109	0	255	0	0
T110	0	360	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168273587	9691	0	0
T19	33933	0	0	0
T31	246312	0	0	0
T32	465207	0	0	0
T33	240707	0	0	0
T34	34113	0	0	0
T35	1449	0	0	0
T36	1011	0	0	0
T37	44216	0	0	0
T38	234093	0	0	0
T44	28919	57	0	0
T45	0	356	0	0
T46	0	247	0	0
T104	0	690	0	0
T105	0	336	0	0
T106	0	253	0	0
T107	0	655	0	0
T108	0	486	0	0
T109	0	237	0	0
T110	0	295	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1168273587	10720	0	0
T19	33933	0	0	0
T31	246312	0	0	0
T32	465207	0	0	0
T33	240707	0	0	0
T34	34113	0	0	0
T35	1449	0	0	0
T36	1011	0	0	0
T37	44216	0	0	0
T38	234093	0	0	0
T44	28919	80	0	0
T45	0	425	0	0
T46	0	397	0	0
T104	0	868	0	0
T105	0	372	0	0
T106	0	275	0	0
T107	0	561	0	0
T108	0	450	0	0
T109	0	317	0	0
T110	0	287	0	0