| T797 |
/workspace/coverage/default/9.sram_ctrl_smoke.4218726316 |
|
|
Mar 19 02:22:43 PM PDT 24 |
Mar 19 02:23:07 PM PDT 24 |
4917322373 ps |
| T798 |
/workspace/coverage/default/38.sram_ctrl_mem_walk.4238814610 |
|
|
Mar 19 02:29:51 PM PDT 24 |
Mar 19 02:34:49 PM PDT 24 |
55052033632 ps |
| T799 |
/workspace/coverage/default/29.sram_ctrl_regwen.2374889158 |
|
|
Mar 19 02:27:21 PM PDT 24 |
Mar 19 02:45:48 PM PDT 24 |
13651293475 ps |
| T800 |
/workspace/coverage/default/16.sram_ctrl_stress_all.1894634440 |
|
|
Mar 19 02:24:14 PM PDT 24 |
Mar 19 03:47:12 PM PDT 24 |
149017529999 ps |
| T801 |
/workspace/coverage/default/39.sram_ctrl_partial_access.596506171 |
|
|
Mar 19 02:29:52 PM PDT 24 |
Mar 19 02:31:30 PM PDT 24 |
10599746240 ps |
| T802 |
/workspace/coverage/default/3.sram_ctrl_lc_escalation.1181839655 |
|
|
Mar 19 02:22:00 PM PDT 24 |
Mar 19 02:22:47 PM PDT 24 |
15464403083 ps |
| T803 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.2987442764 |
|
|
Mar 19 02:26:14 PM PDT 24 |
Mar 19 02:26:26 PM PDT 24 |
216146441 ps |
| T804 |
/workspace/coverage/default/17.sram_ctrl_lc_escalation.2539055251 |
|
|
Mar 19 02:24:31 PM PDT 24 |
Mar 19 02:25:15 PM PDT 24 |
6805109831 ps |
| T805 |
/workspace/coverage/default/43.sram_ctrl_executable.2137144834 |
|
|
Mar 19 02:30:54 PM PDT 24 |
Mar 19 02:40:02 PM PDT 24 |
18038625062 ps |
| T806 |
/workspace/coverage/default/22.sram_ctrl_max_throughput.1193566608 |
|
|
Mar 19 02:25:27 PM PDT 24 |
Mar 19 02:26:40 PM PDT 24 |
3072675817 ps |
| T807 |
/workspace/coverage/default/3.sram_ctrl_ram_cfg.509293978 |
|
|
Mar 19 02:22:03 PM PDT 24 |
Mar 19 02:22:06 PM PDT 24 |
1402225445 ps |
| T808 |
/workspace/coverage/default/18.sram_ctrl_stress_pipeline.3535429626 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:29:35 PM PDT 24 |
17926484597 ps |
| T809 |
/workspace/coverage/default/5.sram_ctrl_stress_pipeline.2443278582 |
|
|
Mar 19 02:22:08 PM PDT 24 |
Mar 19 02:27:19 PM PDT 24 |
16484419855 ps |
| T810 |
/workspace/coverage/default/3.sram_ctrl_bijection.1720557238 |
|
|
Mar 19 02:22:02 PM PDT 24 |
Mar 19 02:39:05 PM PDT 24 |
154103225775 ps |
| T811 |
/workspace/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.247750171 |
|
|
Mar 19 02:22:11 PM PDT 24 |
Mar 19 02:22:48 PM PDT 24 |
4898718930 ps |
| T812 |
/workspace/coverage/default/40.sram_ctrl_max_throughput.4124789669 |
|
|
Mar 19 02:30:06 PM PDT 24 |
Mar 19 02:30:17 PM PDT 24 |
2722924882 ps |
| T813 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.1082278719 |
|
|
Mar 19 02:26:26 PM PDT 24 |
Mar 19 02:31:07 PM PDT 24 |
19625732456 ps |
| T814 |
/workspace/coverage/default/11.sram_ctrl_regwen.1868560982 |
|
|
Mar 19 02:23:12 PM PDT 24 |
Mar 19 02:28:54 PM PDT 24 |
2501520321 ps |
| T815 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.2500404733 |
|
|
Mar 19 02:22:59 PM PDT 24 |
Mar 19 02:25:05 PM PDT 24 |
6462573660 ps |
| T816 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.3394008945 |
|
|
Mar 19 02:21:33 PM PDT 24 |
Mar 19 02:22:44 PM PDT 24 |
38801550855 ps |
| T817 |
/workspace/coverage/default/40.sram_ctrl_mem_partial_access.3226310000 |
|
|
Mar 19 02:30:17 PM PDT 24 |
Mar 19 02:32:59 PM PDT 24 |
25688596746 ps |
| T818 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.1485306186 |
|
|
Mar 19 02:24:47 PM PDT 24 |
Mar 19 02:24:51 PM PDT 24 |
1357490594 ps |
| T819 |
/workspace/coverage/default/30.sram_ctrl_stress_all.2534124040 |
|
|
Mar 19 02:27:35 PM PDT 24 |
Mar 19 04:56:30 PM PDT 24 |
116330510997 ps |
| T820 |
/workspace/coverage/default/18.sram_ctrl_regwen.94607098 |
|
|
Mar 19 02:24:57 PM PDT 24 |
Mar 19 02:52:30 PM PDT 24 |
20755954116 ps |
| T821 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3274317597 |
|
|
Mar 19 02:30:07 PM PDT 24 |
Mar 19 02:52:54 PM PDT 24 |
12883483013 ps |
| T822 |
/workspace/coverage/default/24.sram_ctrl_regwen.1413607867 |
|
|
Mar 19 02:25:54 PM PDT 24 |
Mar 19 02:39:58 PM PDT 24 |
13490973202 ps |
| T77 |
/workspace/coverage/default/42.sram_ctrl_mem_partial_access.4163038529 |
|
|
Mar 19 02:30:48 PM PDT 24 |
Mar 19 02:33:18 PM PDT 24 |
10584229880 ps |
| T823 |
/workspace/coverage/default/35.sram_ctrl_mem_walk.194312540 |
|
|
Mar 19 02:28:59 PM PDT 24 |
Mar 19 02:31:35 PM PDT 24 |
10768442551 ps |
| T824 |
/workspace/coverage/default/26.sram_ctrl_regwen.1441394668 |
|
|
Mar 19 02:26:24 PM PDT 24 |
Mar 19 02:34:04 PM PDT 24 |
11002331050 ps |
| T825 |
/workspace/coverage/default/26.sram_ctrl_access_during_key_req.1786085291 |
|
|
Mar 19 02:26:24 PM PDT 24 |
Mar 19 02:29:52 PM PDT 24 |
15973430678 ps |
| T826 |
/workspace/coverage/default/16.sram_ctrl_lc_escalation.1109725496 |
|
|
Mar 19 02:24:06 PM PDT 24 |
Mar 19 02:25:06 PM PDT 24 |
54803156146 ps |
| T827 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.2925709920 |
|
|
Mar 19 02:31:03 PM PDT 24 |
Mar 19 02:34:57 PM PDT 24 |
12151916838 ps |
| T828 |
/workspace/coverage/default/23.sram_ctrl_partial_access_b2b.1374021225 |
|
|
Mar 19 02:25:37 PM PDT 24 |
Mar 19 02:32:44 PM PDT 24 |
55630465476 ps |
| T829 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.4158332035 |
|
|
Mar 19 02:28:50 PM PDT 24 |
Mar 19 02:29:14 PM PDT 24 |
3456256447 ps |
| T830 |
/workspace/coverage/default/44.sram_ctrl_lc_escalation.2133534969 |
|
|
Mar 19 02:31:11 PM PDT 24 |
Mar 19 02:32:16 PM PDT 24 |
11562800007 ps |
| T831 |
/workspace/coverage/default/6.sram_ctrl_max_throughput.2095444420 |
|
|
Mar 19 02:22:19 PM PDT 24 |
Mar 19 02:22:37 PM PDT 24 |
804404648 ps |
| T832 |
/workspace/coverage/default/33.sram_ctrl_stress_all.353956598 |
|
|
Mar 19 02:28:27 PM PDT 24 |
Mar 19 03:30:59 PM PDT 24 |
385670976621 ps |
| T833 |
/workspace/coverage/default/10.sram_ctrl_bijection.2461557187 |
|
|
Mar 19 02:22:50 PM PDT 24 |
Mar 19 03:04:37 PM PDT 24 |
107987719914 ps |
| T834 |
/workspace/coverage/default/19.sram_ctrl_partial_access.2744801467 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:27:45 PM PDT 24 |
2866061189 ps |
| T835 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.3408507096 |
|
|
Mar 19 02:26:55 PM PDT 24 |
Mar 19 02:30:44 PM PDT 24 |
3421411253 ps |
| T836 |
/workspace/coverage/default/43.sram_ctrl_bijection.214030272 |
|
|
Mar 19 02:30:48 PM PDT 24 |
Mar 19 02:54:28 PM PDT 24 |
487755273544 ps |
| T837 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.2118907081 |
|
|
Mar 19 02:22:01 PM PDT 24 |
Mar 19 02:24:08 PM PDT 24 |
3137367960 ps |
| T838 |
/workspace/coverage/default/33.sram_ctrl_smoke.894789648 |
|
|
Mar 19 02:28:06 PM PDT 24 |
Mar 19 02:28:56 PM PDT 24 |
698304034 ps |
| T839 |
/workspace/coverage/default/43.sram_ctrl_lc_escalation.3171592026 |
|
|
Mar 19 02:30:54 PM PDT 24 |
Mar 19 02:31:29 PM PDT 24 |
23493707187 ps |
| T840 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.737710792 |
|
|
Mar 19 02:31:11 PM PDT 24 |
Mar 19 02:31:14 PM PDT 24 |
1944193400 ps |
| T841 |
/workspace/coverage/default/10.sram_ctrl_ram_cfg.2408577653 |
|
|
Mar 19 02:22:48 PM PDT 24 |
Mar 19 02:22:52 PM PDT 24 |
708242578 ps |
| T842 |
/workspace/coverage/default/38.sram_ctrl_smoke.4053144710 |
|
|
Mar 19 02:29:50 PM PDT 24 |
Mar 19 02:29:58 PM PDT 24 |
3170411822 ps |
| T843 |
/workspace/coverage/default/23.sram_ctrl_executable.2659705861 |
|
|
Mar 19 02:25:47 PM PDT 24 |
Mar 19 02:39:40 PM PDT 24 |
8339705760 ps |
| T844 |
/workspace/coverage/default/42.sram_ctrl_alert_test.3934918333 |
|
|
Mar 19 02:30:46 PM PDT 24 |
Mar 19 02:30:48 PM PDT 24 |
33425996 ps |
| T845 |
/workspace/coverage/default/46.sram_ctrl_max_throughput.3852302872 |
|
|
Mar 19 02:31:45 PM PDT 24 |
Mar 19 02:32:33 PM PDT 24 |
755749190 ps |
| T846 |
/workspace/coverage/default/21.sram_ctrl_executable.2130806020 |
|
|
Mar 19 02:25:06 PM PDT 24 |
Mar 19 02:26:23 PM PDT 24 |
1028038162 ps |
| T847 |
/workspace/coverage/default/13.sram_ctrl_stress_all_with_rand_reset.2937838719 |
|
|
Mar 19 02:23:25 PM PDT 24 |
Mar 19 02:24:17 PM PDT 24 |
2900238829 ps |
| T848 |
/workspace/coverage/default/21.sram_ctrl_throughput_w_partial_write.2165413083 |
|
|
Mar 19 02:25:08 PM PDT 24 |
Mar 19 02:25:48 PM PDT 24 |
1531434808 ps |
| T849 |
/workspace/coverage/default/19.sram_ctrl_multiple_keys.1276780535 |
|
|
Mar 19 02:24:56 PM PDT 24 |
Mar 19 02:34:11 PM PDT 24 |
66399074671 ps |
| T850 |
/workspace/coverage/default/26.sram_ctrl_throughput_w_partial_write.1902458291 |
|
|
Mar 19 02:26:25 PM PDT 24 |
Mar 19 02:26:31 PM PDT 24 |
2740657812 ps |
| T851 |
/workspace/coverage/default/15.sram_ctrl_max_throughput.3207929062 |
|
|
Mar 19 02:23:43 PM PDT 24 |
Mar 19 02:26:05 PM PDT 24 |
1530390897 ps |
| T852 |
/workspace/coverage/default/6.sram_ctrl_mem_partial_access.591186219 |
|
|
Mar 19 02:22:18 PM PDT 24 |
Mar 19 02:24:42 PM PDT 24 |
1596632262 ps |
| T853 |
/workspace/coverage/default/37.sram_ctrl_mem_partial_access.1416140330 |
|
|
Mar 19 02:29:33 PM PDT 24 |
Mar 19 02:30:52 PM PDT 24 |
2624292074 ps |
| T854 |
/workspace/coverage/default/19.sram_ctrl_regwen.1449706347 |
|
|
Mar 19 02:25:03 PM PDT 24 |
Mar 19 02:45:52 PM PDT 24 |
70346550909 ps |
| T855 |
/workspace/coverage/default/14.sram_ctrl_bijection.2686729482 |
|
|
Mar 19 02:23:32 PM PDT 24 |
Mar 19 03:00:08 PM PDT 24 |
142194971352 ps |
| T856 |
/workspace/coverage/default/41.sram_ctrl_partial_access_b2b.3098617724 |
|
|
Mar 19 02:30:24 PM PDT 24 |
Mar 19 02:35:50 PM PDT 24 |
6238493184 ps |
| T857 |
/workspace/coverage/default/46.sram_ctrl_partial_access.1067031807 |
|
|
Mar 19 02:31:39 PM PDT 24 |
Mar 19 02:31:54 PM PDT 24 |
1101356438 ps |
| T858 |
/workspace/coverage/default/45.sram_ctrl_bijection.2146338819 |
|
|
Mar 19 02:31:18 PM PDT 24 |
Mar 19 02:47:08 PM PDT 24 |
242229781176 ps |
| T859 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.1992828850 |
|
|
Mar 19 02:22:09 PM PDT 24 |
Mar 19 02:48:53 PM PDT 24 |
15105975077 ps |
| T860 |
/workspace/coverage/default/33.sram_ctrl_access_during_key_req.2333836626 |
|
|
Mar 19 02:28:27 PM PDT 24 |
Mar 19 02:38:06 PM PDT 24 |
7652151721 ps |
| T861 |
/workspace/coverage/default/27.sram_ctrl_partial_access_b2b.2041923742 |
|
|
Mar 19 02:26:46 PM PDT 24 |
Mar 19 02:32:43 PM PDT 24 |
213416337964 ps |
| T862 |
/workspace/coverage/default/9.sram_ctrl_ram_cfg.3884797092 |
|
|
Mar 19 02:22:39 PM PDT 24 |
Mar 19 02:22:42 PM PDT 24 |
362557976 ps |
| T863 |
/workspace/coverage/default/18.sram_ctrl_stress_all.285594136 |
|
|
Mar 19 02:24:52 PM PDT 24 |
Mar 19 03:52:10 PM PDT 24 |
49353121867 ps |
| T864 |
/workspace/coverage/default/22.sram_ctrl_mem_walk.3809744658 |
|
|
Mar 19 02:25:31 PM PDT 24 |
Mar 19 02:29:35 PM PDT 24 |
4114264321 ps |
| T865 |
/workspace/coverage/default/14.sram_ctrl_partial_access_b2b.384395074 |
|
|
Mar 19 02:23:25 PM PDT 24 |
Mar 19 02:30:11 PM PDT 24 |
61649048488 ps |
| T866 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2405639342 |
|
|
Mar 19 02:31:48 PM PDT 24 |
Mar 19 02:47:02 PM PDT 24 |
9465447867 ps |
| T867 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2649210319 |
|
|
Mar 19 02:22:49 PM PDT 24 |
Mar 19 02:24:11 PM PDT 24 |
778204710 ps |
| T868 |
/workspace/coverage/default/7.sram_ctrl_throughput_w_partial_write.1876186473 |
|
|
Mar 19 02:22:18 PM PDT 24 |
Mar 19 02:22:38 PM PDT 24 |
1966425846 ps |
| T869 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1562448811 |
|
|
Mar 19 02:24:48 PM PDT 24 |
Mar 19 02:26:31 PM PDT 24 |
3092449298 ps |
| T870 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1953723199 |
|
|
Mar 19 02:31:04 PM PDT 24 |
Mar 19 02:31:14 PM PDT 24 |
1349053513 ps |
| T871 |
/workspace/coverage/default/48.sram_ctrl_smoke.226772172 |
|
|
Mar 19 02:32:11 PM PDT 24 |
Mar 19 02:32:25 PM PDT 24 |
1922326960 ps |
| T872 |
/workspace/coverage/default/0.sram_ctrl_alert_test.1458844020 |
|
|
Mar 19 02:21:47 PM PDT 24 |
Mar 19 02:21:48 PM PDT 24 |
17985234 ps |
| T873 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.74755790 |
|
|
Mar 19 02:22:02 PM PDT 24 |
Mar 19 02:24:29 PM PDT 24 |
3103319444 ps |
| T874 |
/workspace/coverage/default/17.sram_ctrl_partial_access.4165623858 |
|
|
Mar 19 02:24:14 PM PDT 24 |
Mar 19 02:24:18 PM PDT 24 |
390714863 ps |
| T875 |
/workspace/coverage/default/0.sram_ctrl_throughput_w_partial_write.4109944482 |
|
|
Mar 19 02:21:31 PM PDT 24 |
Mar 19 02:21:38 PM PDT 24 |
846445483 ps |
| T876 |
/workspace/coverage/default/7.sram_ctrl_mem_walk.1201917313 |
|
|
Mar 19 02:22:31 PM PDT 24 |
Mar 19 02:26:47 PM PDT 24 |
43772823247 ps |
| T877 |
/workspace/coverage/default/8.sram_ctrl_stress_pipeline.3112489642 |
|
|
Mar 19 02:22:33 PM PDT 24 |
Mar 19 02:26:50 PM PDT 24 |
28503304403 ps |
| T878 |
/workspace/coverage/default/12.sram_ctrl_lc_escalation.3678803147 |
|
|
Mar 19 02:23:13 PM PDT 24 |
Mar 19 02:24:23 PM PDT 24 |
11135933924 ps |
| T879 |
/workspace/coverage/default/44.sram_ctrl_stress_pipeline.3322023156 |
|
|
Mar 19 02:31:05 PM PDT 24 |
Mar 19 02:35:40 PM PDT 24 |
16867125121 ps |
| T880 |
/workspace/coverage/default/3.sram_ctrl_regwen.905770030 |
|
|
Mar 19 02:21:59 PM PDT 24 |
Mar 19 02:49:51 PM PDT 24 |
48222509538 ps |
| T881 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.3359159337 |
|
|
Mar 19 02:29:43 PM PDT 24 |
Mar 19 02:33:21 PM PDT 24 |
4472490496 ps |
| T882 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.2213754792 |
|
|
Mar 19 02:27:57 PM PDT 24 |
Mar 19 02:30:49 PM PDT 24 |
5836301776 ps |
| T883 |
/workspace/coverage/default/38.sram_ctrl_ram_cfg.552717983 |
|
|
Mar 19 02:29:50 PM PDT 24 |
Mar 19 02:29:54 PM PDT 24 |
354303044 ps |
| T884 |
/workspace/coverage/default/25.sram_ctrl_max_throughput.3908850591 |
|
|
Mar 19 02:26:08 PM PDT 24 |
Mar 19 02:26:19 PM PDT 24 |
725021394 ps |
| T885 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.1251878161 |
|
|
Mar 19 02:30:19 PM PDT 24 |
Mar 19 02:31:38 PM PDT 24 |
6053881314 ps |
| T886 |
/workspace/coverage/default/16.sram_ctrl_throughput_w_partial_write.3471445818 |
|
|
Mar 19 02:24:05 PM PDT 24 |
Mar 19 02:24:37 PM PDT 24 |
2858971921 ps |
| T887 |
/workspace/coverage/default/5.sram_ctrl_bijection.2320052129 |
|
|
Mar 19 02:22:10 PM PDT 24 |
Mar 19 02:32:57 PM PDT 24 |
157981697651 ps |
| T888 |
/workspace/coverage/default/13.sram_ctrl_alert_test.2277050812 |
|
|
Mar 19 02:23:27 PM PDT 24 |
Mar 19 02:23:28 PM PDT 24 |
37975384 ps |
| T889 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.1107941439 |
|
|
Mar 19 02:29:07 PM PDT 24 |
Mar 19 02:55:09 PM PDT 24 |
50909766144 ps |
| T890 |
/workspace/coverage/default/32.sram_ctrl_lc_escalation.1780414509 |
|
|
Mar 19 02:28:05 PM PDT 24 |
Mar 19 02:28:49 PM PDT 24 |
5951627783 ps |
| T891 |
/workspace/coverage/default/6.sram_ctrl_smoke.951731061 |
|
|
Mar 19 02:22:17 PM PDT 24 |
Mar 19 02:22:38 PM PDT 24 |
3043933339 ps |
| T892 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3158817483 |
|
|
Mar 19 02:27:07 PM PDT 24 |
Mar 19 02:32:16 PM PDT 24 |
8193752193 ps |
| T893 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.138565647 |
|
|
Mar 19 02:24:05 PM PDT 24 |
Mar 19 02:26:43 PM PDT 24 |
41324160418 ps |
| T894 |
/workspace/coverage/default/29.sram_ctrl_stress_pipeline.2800097490 |
|
|
Mar 19 02:27:07 PM PDT 24 |
Mar 19 02:33:00 PM PDT 24 |
5330849055 ps |
| T895 |
/workspace/coverage/default/18.sram_ctrl_mem_partial_access.3762654592 |
|
|
Mar 19 02:24:52 PM PDT 24 |
Mar 19 02:26:23 PM PDT 24 |
5419836065 ps |
| T896 |
/workspace/coverage/default/35.sram_ctrl_stress_all.3062421681 |
|
|
Mar 19 02:29:08 PM PDT 24 |
Mar 19 04:27:47 PM PDT 24 |
169137797714 ps |
| T897 |
/workspace/coverage/default/25.sram_ctrl_stress_all.2747922007 |
|
|
Mar 19 02:26:17 PM PDT 24 |
Mar 19 04:38:33 PM PDT 24 |
350374691554 ps |
| T898 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3677383432 |
|
|
Mar 19 02:23:56 PM PDT 24 |
Mar 19 02:29:15 PM PDT 24 |
5013260567 ps |
| T899 |
/workspace/coverage/default/43.sram_ctrl_regwen.391542214 |
|
|
Mar 19 02:30:53 PM PDT 24 |
Mar 19 02:34:21 PM PDT 24 |
9406905558 ps |
| T900 |
/workspace/coverage/default/42.sram_ctrl_executable.301094678 |
|
|
Mar 19 02:30:46 PM PDT 24 |
Mar 19 02:39:17 PM PDT 24 |
10983831068 ps |
| T901 |
/workspace/coverage/default/7.sram_ctrl_executable.2220477555 |
|
|
Mar 19 02:22:29 PM PDT 24 |
Mar 19 02:37:32 PM PDT 24 |
16324946467 ps |
| T902 |
/workspace/coverage/default/44.sram_ctrl_regwen.2670467623 |
|
|
Mar 19 02:31:11 PM PDT 24 |
Mar 19 02:54:19 PM PDT 24 |
21951976656 ps |
| T903 |
/workspace/coverage/default/28.sram_ctrl_stress_all.2475746688 |
|
|
Mar 19 02:27:09 PM PDT 24 |
Mar 19 04:54:18 PM PDT 24 |
340639918800 ps |
| T904 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3683250421 |
|
|
Mar 19 02:29:33 PM PDT 24 |
Mar 19 02:30:37 PM PDT 24 |
790999001 ps |
| T905 |
/workspace/coverage/default/17.sram_ctrl_stress_all.3963102186 |
|
|
Mar 19 02:24:47 PM PDT 24 |
Mar 19 03:02:53 PM PDT 24 |
137173996341 ps |
| T906 |
/workspace/coverage/default/33.sram_ctrl_partial_access_b2b.1014276954 |
|
|
Mar 19 02:28:16 PM PDT 24 |
Mar 19 02:33:22 PM PDT 24 |
15440669624 ps |
| T907 |
/workspace/coverage/default/27.sram_ctrl_access_during_key_req.2113980213 |
|
|
Mar 19 02:26:43 PM PDT 24 |
Mar 19 02:40:07 PM PDT 24 |
51279579469 ps |
| T908 |
/workspace/coverage/default/30.sram_ctrl_throughput_w_partial_write.4184855788 |
|
|
Mar 19 02:27:24 PM PDT 24 |
Mar 19 02:27:33 PM PDT 24 |
2735994434 ps |
| T909 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4024443692 |
|
|
Mar 19 02:32:42 PM PDT 24 |
Mar 19 02:32:43 PM PDT 24 |
13369394 ps |
| T910 |
/workspace/coverage/default/4.sram_ctrl_ram_cfg.1639663862 |
|
|
Mar 19 02:22:11 PM PDT 24 |
Mar 19 02:22:15 PM PDT 24 |
729512067 ps |
| T911 |
/workspace/coverage/default/1.sram_ctrl_mem_partial_access.3718675404 |
|
|
Mar 19 02:21:47 PM PDT 24 |
Mar 19 02:24:17 PM PDT 24 |
4758425770 ps |
| T912 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.2468837145 |
|
|
Mar 19 02:24:58 PM PDT 24 |
Mar 19 02:28:00 PM PDT 24 |
943422473 ps |
| T913 |
/workspace/coverage/default/6.sram_ctrl_throughput_w_partial_write.4158780144 |
|
|
Mar 19 02:22:18 PM PDT 24 |
Mar 19 02:22:27 PM PDT 24 |
828560552 ps |
| T914 |
/workspace/coverage/default/5.sram_ctrl_lc_escalation.591857737 |
|
|
Mar 19 02:22:13 PM PDT 24 |
Mar 19 02:22:22 PM PDT 24 |
1548073900 ps |
| T915 |
/workspace/coverage/default/49.sram_ctrl_regwen.2018501785 |
|
|
Mar 19 02:32:33 PM PDT 24 |
Mar 19 03:06:52 PM PDT 24 |
35119806827 ps |
| T916 |
/workspace/coverage/default/18.sram_ctrl_executable.3911588406 |
|
|
Mar 19 02:24:58 PM PDT 24 |
Mar 19 02:33:50 PM PDT 24 |
15281409323 ps |
| T917 |
/workspace/coverage/default/49.sram_ctrl_stress_all.2255943408 |
|
|
Mar 19 02:32:41 PM PDT 24 |
Mar 19 03:05:41 PM PDT 24 |
88830217819 ps |
| T918 |
/workspace/coverage/default/49.sram_ctrl_smoke.3432546588 |
|
|
Mar 19 02:32:26 PM PDT 24 |
Mar 19 02:32:37 PM PDT 24 |
1300540870 ps |
| T919 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.3597067769 |
|
|
Mar 19 02:30:33 PM PDT 24 |
Mar 19 02:33:21 PM PDT 24 |
7186571856 ps |
| T920 |
/workspace/coverage/default/31.sram_ctrl_executable.1446875303 |
|
|
Mar 19 02:27:46 PM PDT 24 |
Mar 19 03:00:17 PM PDT 24 |
243186047742 ps |
| T921 |
/workspace/coverage/default/2.sram_ctrl_multiple_keys.2516894976 |
|
|
Mar 19 02:22:02 PM PDT 24 |
Mar 19 02:28:36 PM PDT 24 |
34006242093 ps |
| T922 |
/workspace/coverage/default/4.sram_ctrl_mem_walk.2422487085 |
|
|
Mar 19 02:22:11 PM PDT 24 |
Mar 19 02:24:19 PM PDT 24 |
4200287568 ps |
| T923 |
/workspace/coverage/default/26.sram_ctrl_smoke.626818604 |
|
|
Mar 19 02:26:24 PM PDT 24 |
Mar 19 02:26:40 PM PDT 24 |
830359395 ps |
| T924 |
/workspace/coverage/default/5.sram_ctrl_stress_all.50148397 |
|
|
Mar 19 02:22:12 PM PDT 24 |
Mar 19 03:34:39 PM PDT 24 |
57032890354 ps |
| T925 |
/workspace/coverage/default/14.sram_ctrl_ram_cfg.1775448254 |
|
|
Mar 19 02:23:40 PM PDT 24 |
Mar 19 02:23:43 PM PDT 24 |
1348756814 ps |
| T926 |
/workspace/coverage/default/24.sram_ctrl_smoke.315904615 |
|
|
Mar 19 02:25:46 PM PDT 24 |
Mar 19 02:26:03 PM PDT 24 |
1119465382 ps |
| T927 |
/workspace/coverage/default/0.sram_ctrl_stress_pipeline.55182133 |
|
|
Mar 19 02:21:32 PM PDT 24 |
Mar 19 02:26:38 PM PDT 24 |
4334734948 ps |
| T928 |
/workspace/coverage/default/2.sram_ctrl_partial_access_b2b.1546455771 |
|
|
Mar 19 02:22:00 PM PDT 24 |
Mar 19 02:27:56 PM PDT 24 |
17203768572 ps |
| T929 |
/workspace/coverage/default/24.sram_ctrl_alert_test.551165471 |
|
|
Mar 19 02:25:59 PM PDT 24 |
Mar 19 02:26:00 PM PDT 24 |
28155058 ps |
| T930 |
/workspace/coverage/default/18.sram_ctrl_access_during_key_req.2386196769 |
|
|
Mar 19 02:24:57 PM PDT 24 |
Mar 19 02:32:11 PM PDT 24 |
7476485824 ps |
| T931 |
/workspace/coverage/default/14.sram_ctrl_mem_walk.1847394656 |
|
|
Mar 19 02:23:36 PM PDT 24 |
Mar 19 02:28:35 PM PDT 24 |
17876127544 ps |
| T932 |
/workspace/coverage/default/28.sram_ctrl_partial_access.1925952586 |
|
|
Mar 19 02:27:07 PM PDT 24 |
Mar 19 02:27:16 PM PDT 24 |
596809377 ps |
| T933 |
/workspace/coverage/default/46.sram_ctrl_partial_access_b2b.4040911796 |
|
|
Mar 19 02:31:40 PM PDT 24 |
Mar 19 02:37:28 PM PDT 24 |
26762466418 ps |
| T934 |
/workspace/coverage/default/18.sram_ctrl_smoke.282336502 |
|
|
Mar 19 02:24:47 PM PDT 24 |
Mar 19 02:24:59 PM PDT 24 |
3386771064 ps |
| T935 |
/workspace/coverage/default/25.sram_ctrl_mem_partial_access.2973198736 |
|
|
Mar 19 02:26:18 PM PDT 24 |
Mar 19 02:28:48 PM PDT 24 |
20719616228 ps |
| T936 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1298640282 |
|
|
Mar 19 02:23:15 PM PDT 24 |
Mar 19 02:23:27 PM PDT 24 |
2747430284 ps |
| T937 |
/workspace/coverage/default/4.sram_ctrl_executable.1867295847 |
|
|
Mar 19 02:22:11 PM PDT 24 |
Mar 19 02:26:51 PM PDT 24 |
11037653592 ps |
| T938 |
/workspace/coverage/default/20.sram_ctrl_alert_test.4038431704 |
|
|
Mar 19 02:25:04 PM PDT 24 |
Mar 19 02:25:05 PM PDT 24 |
33176000 ps |
| T939 |
/workspace/coverage/default/24.sram_ctrl_partial_access.2801300728 |
|
|
Mar 19 02:25:46 PM PDT 24 |
Mar 19 02:25:53 PM PDT 24 |
1468855784 ps |
| T940 |
/workspace/coverage/default/16.sram_ctrl_max_throughput.883971610 |
|
|
Mar 19 02:24:06 PM PDT 24 |
Mar 19 02:26:25 PM PDT 24 |
3068443009 ps |
| T941 |
/workspace/coverage/default/41.sram_ctrl_stress_all_with_rand_reset.455808155 |
|
|
Mar 19 02:30:31 PM PDT 24 |
Mar 19 02:31:07 PM PDT 24 |
7889099409 ps |
| T942 |
/workspace/coverage/default/12.sram_ctrl_alert_test.971197373 |
|
|
Mar 19 02:23:17 PM PDT 24 |
Mar 19 02:23:18 PM PDT 24 |
43394198 ps |
| T943 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.1076070586 |
|
|
Mar 19 02:30:00 PM PDT 24 |
Mar 19 02:30:04 PM PDT 24 |
2405085463 ps |
| T944 |
/workspace/coverage/default/37.sram_ctrl_regwen.151558513 |
|
|
Mar 19 02:29:33 PM PDT 24 |
Mar 19 03:01:29 PM PDT 24 |
17162433563 ps |
| T945 |
/workspace/coverage/default/23.sram_ctrl_multiple_keys.782202872 |
|
|
Mar 19 02:25:36 PM PDT 24 |
Mar 19 02:33:50 PM PDT 24 |
69072476228 ps |
| T100 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1583621247 |
|
|
Mar 19 12:43:27 PM PDT 24 |
Mar 19 12:43:28 PM PDT 24 |
47331976 ps |
| T90 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.2182702402 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:43 PM PDT 24 |
16700463 ps |
| T946 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1908685230 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:43:36 PM PDT 24 |
114260718 ps |
| T947 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2874478701 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:35 PM PDT 24 |
38970161 ps |
| T91 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1357598811 |
|
|
Mar 19 12:43:38 PM PDT 24 |
Mar 19 12:43:39 PM PDT 24 |
17833958 ps |
| T51 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.4025769073 |
|
|
Mar 19 12:44:01 PM PDT 24 |
Mar 19 12:44:03 PM PDT 24 |
17282778 ps |
| T123 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.1224192001 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
11424112 ps |
| T948 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_mem_rw_with_rand_reset.154087602 |
|
|
Mar 19 12:43:30 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
359873540 ps |
| T52 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.536895439 |
|
|
Mar 19 12:43:38 PM PDT 24 |
Mar 19 12:44:28 PM PDT 24 |
29554318832 ps |
| T53 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_rw.482997797 |
|
|
Mar 19 12:43:36 PM PDT 24 |
Mar 19 12:43:37 PM PDT 24 |
54245772 ps |
| T54 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.1895427103 |
|
|
Mar 19 12:43:43 PM PDT 24 |
Mar 19 12:44:38 PM PDT 24 |
23453578775 ps |
| T949 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.1917481844 |
|
|
Mar 19 12:43:36 PM PDT 24 |
Mar 19 12:43:40 PM PDT 24 |
360363153 ps |
| T92 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.1238313830 |
|
|
Mar 19 12:43:58 PM PDT 24 |
Mar 19 12:44:25 PM PDT 24 |
14782397863 ps |
| T950 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.1932190517 |
|
|
Mar 19 12:43:43 PM PDT 24 |
Mar 19 12:43:47 PM PDT 24 |
128795358 ps |
| T951 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.492459652 |
|
|
Mar 19 12:43:56 PM PDT 24 |
Mar 19 12:44:01 PM PDT 24 |
138133664 ps |
| T952 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.367855763 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:33 PM PDT 24 |
254546653 ps |
| T55 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.3617399691 |
|
|
Mar 19 12:43:46 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
20169012 ps |
| T93 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.3880314306 |
|
|
Mar 19 12:43:53 PM PDT 24 |
Mar 19 12:43:54 PM PDT 24 |
58845912 ps |
| T56 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3669387370 |
|
|
Mar 19 12:43:29 PM PDT 24 |
Mar 19 12:43:31 PM PDT 24 |
15360387 ps |
| T57 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.972967293 |
|
|
Mar 19 12:43:47 PM PDT 24 |
Mar 19 12:43:48 PM PDT 24 |
12915884 ps |
| T101 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2157301363 |
|
|
Mar 19 12:43:43 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
1774788819 ps |
| T58 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1339583515 |
|
|
Mar 19 12:43:41 PM PDT 24 |
Mar 19 12:44:37 PM PDT 24 |
28214918359 ps |
| T953 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1181951247 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:45 PM PDT 24 |
295087561 ps |
| T954 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.4204859566 |
|
|
Mar 19 12:43:57 PM PDT 24 |
Mar 19 12:44:01 PM PDT 24 |
186851239 ps |
| T102 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.3938581771 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
388148894 ps |
| T94 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3970594816 |
|
|
Mar 19 12:43:36 PM PDT 24 |
Mar 19 12:43:36 PM PDT 24 |
13197393 ps |
| T955 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.679174247 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:43:37 PM PDT 24 |
116023447 ps |
| T59 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.260269508 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:44:11 PM PDT 24 |
13927417291 ps |
| T60 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.792627898 |
|
|
Mar 19 12:44:02 PM PDT 24 |
Mar 19 12:44:03 PM PDT 24 |
18847048 ps |
| T64 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.556108393 |
|
|
Mar 19 12:43:36 PM PDT 24 |
Mar 19 12:44:33 PM PDT 24 |
28186674501 ps |
| T956 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.1963141542 |
|
|
Mar 19 12:43:45 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
20875755 ps |
| T957 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2029205620 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
364815720 ps |
| T958 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_same_csr_outstanding.4279769795 |
|
|
Mar 19 12:43:41 PM PDT 24 |
Mar 19 12:43:42 PM PDT 24 |
23142118 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.2759492268 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:35 PM PDT 24 |
423967900 ps |
| T959 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.3984846450 |
|
|
Mar 19 12:43:56 PM PDT 24 |
Mar 19 12:44:22 PM PDT 24 |
3912381769 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3888507252 |
|
|
Mar 19 12:43:54 PM PDT 24 |
Mar 19 12:43:55 PM PDT 24 |
48575872 ps |
| T961 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.628153519 |
|
|
Mar 19 12:43:41 PM PDT 24 |
Mar 19 12:44:35 PM PDT 24 |
28174246058 ps |
| T962 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1698822387 |
|
|
Mar 19 12:43:56 PM PDT 24 |
Mar 19 12:44:00 PM PDT 24 |
61247487 ps |
| T963 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.1982499874 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:45 PM PDT 24 |
28873762 ps |
| T65 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.2089162811 |
|
|
Mar 19 12:43:37 PM PDT 24 |
Mar 19 12:43:38 PM PDT 24 |
13989476 ps |
| T964 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1795032571 |
|
|
Mar 19 12:43:45 PM PDT 24 |
Mar 19 12:43:49 PM PDT 24 |
1369716813 ps |
| T965 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_mem_rw_with_rand_reset.4083936894 |
|
|
Mar 19 12:43:35 PM PDT 24 |
Mar 19 12:43:40 PM PDT 24 |
368201178 ps |
| T113 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3271026561 |
|
|
Mar 19 12:43:49 PM PDT 24 |
Mar 19 12:43:52 PM PDT 24 |
360418422 ps |
| T966 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_mem_rw_with_rand_reset.842209758 |
|
|
Mar 19 12:43:38 PM PDT 24 |
Mar 19 12:43:43 PM PDT 24 |
1468962255 ps |
| T967 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.673040277 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:43:36 PM PDT 24 |
50314728 ps |
| T968 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.1837424727 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
38020907 ps |
| T969 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.2962514004 |
|
|
Mar 19 12:43:30 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
41623001 ps |
| T116 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3286348871 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
1227256299 ps |
| T114 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3286597599 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
397958211 ps |
| T970 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.638943329 |
|
|
Mar 19 12:43:56 PM PDT 24 |
Mar 19 12:44:00 PM PDT 24 |
365120743 ps |
| T971 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.4151035494 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:33 PM PDT 24 |
32730960 ps |
| T972 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1454877957 |
|
|
Mar 19 12:43:46 PM PDT 24 |
Mar 19 12:43:47 PM PDT 24 |
16717921 ps |
| T973 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.2033911267 |
|
|
Mar 19 12:43:51 PM PDT 24 |
Mar 19 12:43:52 PM PDT 24 |
36685218 ps |
| T974 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.4062568871 |
|
|
Mar 19 12:43:38 PM PDT 24 |
Mar 19 12:44:33 PM PDT 24 |
28196262289 ps |
| T975 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.500422418 |
|
|
Mar 19 12:43:45 PM PDT 24 |
Mar 19 12:43:48 PM PDT 24 |
216625814 ps |
| T976 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.2233391555 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:43 PM PDT 24 |
14447777 ps |
| T977 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.1190999444 |
|
|
Mar 19 12:43:52 PM PDT 24 |
Mar 19 12:43:53 PM PDT 24 |
91494103 ps |
| T978 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.3737194826 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:32 PM PDT 24 |
22641186 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2229865807 |
|
|
Mar 19 12:43:50 PM PDT 24 |
Mar 19 12:43:52 PM PDT 24 |
181759896 ps |
| T980 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.2294092866 |
|
|
Mar 19 12:43:38 PM PDT 24 |
Mar 19 12:43:39 PM PDT 24 |
25086812 ps |
| T981 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.4277907736 |
|
|
Mar 19 12:43:39 PM PDT 24 |
Mar 19 12:43:40 PM PDT 24 |
80020074 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2509999015 |
|
|
Mar 19 12:43:48 PM PDT 24 |
Mar 19 12:43:52 PM PDT 24 |
36871231 ps |
| T117 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.3772888134 |
|
|
Mar 19 12:43:39 PM PDT 24 |
Mar 19 12:43:41 PM PDT 24 |
385286546 ps |
| T983 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.1020964368 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
15838874 ps |
| T984 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2018923175 |
|
|
Mar 19 12:43:57 PM PDT 24 |
Mar 19 12:43:58 PM PDT 24 |
15798281 ps |
| T115 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.5401345 |
|
|
Mar 19 12:43:54 PM PDT 24 |
Mar 19 12:43:56 PM PDT 24 |
396328533 ps |
| T66 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_passthru_mem_tl_intg_err.3066488249 |
|
|
Mar 19 12:43:32 PM PDT 24 |
Mar 19 12:43:58 PM PDT 24 |
5672213399 ps |
| T67 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.249290087 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
14319825 ps |
| T985 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.1775903437 |
|
|
Mar 19 12:43:47 PM PDT 24 |
Mar 19 12:43:51 PM PDT 24 |
758913780 ps |
| T986 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.38060507 |
|
|
Mar 19 12:43:27 PM PDT 24 |
Mar 19 12:43:30 PM PDT 24 |
558952479 ps |
| T987 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3095436967 |
|
|
Mar 19 12:43:40 PM PDT 24 |
Mar 19 12:43:44 PM PDT 24 |
376349179 ps |
| T119 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3067967767 |
|
|
Mar 19 12:43:43 PM PDT 24 |
Mar 19 12:43:45 PM PDT 24 |
95722394 ps |
| T68 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1751791119 |
|
|
Mar 19 12:43:53 PM PDT 24 |
Mar 19 12:43:54 PM PDT 24 |
13619885 ps |
| T988 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2576875755 |
|
|
Mar 19 12:43:36 PM PDT 24 |
Mar 19 12:43:37 PM PDT 24 |
74942104 ps |
| T989 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1941304034 |
|
|
Mar 19 12:43:32 PM PDT 24 |
Mar 19 12:43:59 PM PDT 24 |
14861671821 ps |
| T990 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_mem_rw_with_rand_reset.3017918712 |
|
|
Mar 19 12:43:35 PM PDT 24 |
Mar 19 12:43:39 PM PDT 24 |
1817588936 ps |
| T991 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.3711213781 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:45 PM PDT 24 |
14987420 ps |
| T992 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3333136798 |
|
|
Mar 19 12:43:32 PM PDT 24 |
Mar 19 12:43:33 PM PDT 24 |
40022893 ps |
| T118 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3721696379 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:32 PM PDT 24 |
220694528 ps |
| T993 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.630045555 |
|
|
Mar 19 12:43:28 PM PDT 24 |
Mar 19 12:43:32 PM PDT 24 |
155264275 ps |
| T78 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.733525846 |
|
|
Mar 19 12:44:02 PM PDT 24 |
Mar 19 12:44:32 PM PDT 24 |
7846242224 ps |
| T994 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1353082373 |
|
|
Mar 19 12:43:46 PM PDT 24 |
Mar 19 12:43:50 PM PDT 24 |
2267184956 ps |
| T995 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.294242134 |
|
|
Mar 19 12:43:41 PM PDT 24 |
Mar 19 12:43:42 PM PDT 24 |
100212370 ps |
| T996 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.2701921640 |
|
|
Mar 19 12:43:44 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
658704670 ps |
| T997 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.351613726 |
|
|
Mar 19 12:43:49 PM PDT 24 |
Mar 19 12:43:51 PM PDT 24 |
335115161 ps |
| T998 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3056538898 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:44 PM PDT 24 |
538146302 ps |
| T999 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2243575431 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:43:39 PM PDT 24 |
1728261297 ps |
| T1000 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.2128297271 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:36 PM PDT 24 |
210723741 ps |
| T1001 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.349039405 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:35 PM PDT 24 |
395275925 ps |
| T121 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.204460123 |
|
|
Mar 19 12:43:26 PM PDT 24 |
Mar 19 12:43:28 PM PDT 24 |
205795698 ps |
| T79 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.3757527550 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:58 PM PDT 24 |
3810636241 ps |
| T1002 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.751497313 |
|
|
Mar 19 12:43:48 PM PDT 24 |
Mar 19 12:43:49 PM PDT 24 |
23784524 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.565865455 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
18711297 ps |
| T80 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1195463612 |
|
|
Mar 19 12:43:34 PM PDT 24 |
Mar 19 12:44:23 PM PDT 24 |
10391472990 ps |
| T81 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.127418651 |
|
|
Mar 19 12:43:39 PM PDT 24 |
Mar 19 12:44:31 PM PDT 24 |
7685479478 ps |
| T1004 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.1401388059 |
|
|
Mar 19 12:43:32 PM PDT 24 |
Mar 19 12:43:32 PM PDT 24 |
53363286 ps |
| T1005 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2915371709 |
|
|
Mar 19 12:43:42 PM PDT 24 |
Mar 19 12:43:46 PM PDT 24 |
1431414984 ps |
| T1006 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3857751591 |
|
|
Mar 19 12:43:33 PM PDT 24 |
Mar 19 12:43:34 PM PDT 24 |
32666580 ps |
| T1007 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.3792939122 |
|
|
Mar 19 12:43:31 PM PDT 24 |
Mar 19 12:43:35 PM PDT 24 |
365404424 ps |
| T1008 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_errors.1890448875 |
|
|
Mar 19 12:43:56 PM PDT 24 |
Mar 19 12:44:00 PM PDT 24 |
148553047 ps |