Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16322095	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

151359798

1

T1

927

T3

116991

T4

1620

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	82496878	1			T1	2364		T3	64162		T4	4394
values[0x0]	40968033	1			T1	789		T3	31110		T4	1459
values[0x1]	44216982	1			T1	1556		T3	33226		T4	2984

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8292923	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

159388970

1

T1

2839

T3

122801

T4

5256

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	519460	1			T1	12		T3	541		T4	44
valid_sources[0x01]	550799	1			T1	18		T3	506		T4	41
valid_sources[0x02]	558649	1			T1	9		T3	480		T4	29
valid_sources[0x03]	622117	1			T1	57		T3	499		T4	35
valid_sources[0x04]	515770	1			T1	3		T3	509		T4	34
valid_sources[0x05]	635642	1			T1	25		T3	487		T4	33
valid_sources[0x06]	560040	1			T1	19		T3	485		T4	34
valid_sources[0x07]	727806	1			T1	10		T3	452		T4	27
valid_sources[0x08]	557988	1			T1	1		T3	549		T4	27
valid_sources[0x09]	521073	1			T1	20		T3	509		T4	29
valid_sources[0x0a]	541530	1			T1	14		T3	462		T4	37
valid_sources[0x0b]	587928	1			T1	14		T3	502		T4	34
valid_sources[0x0c]	582891	1			T1	10		T3	530		T4	31
valid_sources[0x0d]	523895	1			T1	38		T3	492		T4	33
valid_sources[0x0e]	523836	1			T1	27		T3	448		T4	45
valid_sources[0x0f]	625885	1			T1	26		T3	512		T4	38
valid_sources[0x10]	539546	1			T1	14		T3	539		T4	31
valid_sources[0x11]	2164175	1			T1	9		T3	498		T4	17
valid_sources[0x12]	620590	1			T1	22		T3	488		T4	24
valid_sources[0x13]	542488	1			T1	49		T3	503		T4	36
valid_sources[0x14]	580999	1			T1	40		T3	478		T4	37
valid_sources[0x15]	573650	1			T1	8		T3	468		T4	35
valid_sources[0x16]	545749	1			T1	41		T3	453		T4	36
valid_sources[0x17]	549692	1			T1	42		T3	487		T4	35
valid_sources[0x18]	571914	1			T1	28		T3	502		T4	43
valid_sources[0x19]	524764	1			T1	21		T3	561		T4	51
valid_sources[0x1a]	1349963	1			T1	1		T3	495		T4	47
valid_sources[0x1b]	538955	1			T1	18		T3	555		T4	27
valid_sources[0x1c]	532233	1			T1	27		T3	538		T4	32
valid_sources[0x1d]	518027	1			T1	26		T3	530		T4	36
valid_sources[0x1e]	532254	1			T1	34		T3	488		T4	30
valid_sources[0x1f]	570287	1			T1	5		T3	538		T4	33
valid_sources[0x20]	521220	1			T1	14		T3	520		T4	38
valid_sources[0x21]	538349	1			T1	39		T3	483		T4	30
valid_sources[0x22]	545748	1			T1	2		T3	518		T4	32
valid_sources[0x23]	536791	1			T1	16		T3	498		T4	24
valid_sources[0x24]	549762	1			T1	15		T3	468		T4	31
valid_sources[0x25]	563896	1			T1	58		T3	482		T4	30
valid_sources[0x26]	533386	1			T1	30		T3	444		T4	25
valid_sources[0x27]	559182	1			T1	17		T3	506		T4	28
valid_sources[0x28]	557634	1			T1	39		T3	522		T4	38
valid_sources[0x29]	534055	1			T1	40		T3	469		T4	31
valid_sources[0x2a]	565604	1			T1	3		T3	526		T4	37
valid_sources[0x2b]	568378	1			T1	3		T3	502		T4	51
valid_sources[0x2c]	517435	1			T1	25		T3	524		T4	38
valid_sources[0x2d]	549598	1			T1	72		T3	465		T4	33
valid_sources[0x2e]	582544	1			T1	14		T3	541		T4	46
valid_sources[0x2f]	1511119	1			T1	45		T3	444		T4	33
valid_sources[0x30]	528655	1			T1	41		T3	492		T4	27
valid_sources[0x31]	769675	1			T1	15		T3	496		T4	38
valid_sources[0x32]	1977594	1			T1	47		T3	484		T4	36
valid_sources[0x33]	590509	1			T1	4		T3	452		T4	33
valid_sources[0x34]	550790	1			T1	8		T3	476		T4	36
valid_sources[0x35]	715581	1			T1	32		T3	486		T4	32
valid_sources[0x36]	528652	1			T1	9		T3	519		T4	23
valid_sources[0x37]	582011	1			T1	27		T3	501		T4	34
valid_sources[0x38]	541405	1			T1	1		T3	485		T4	26
valid_sources[0x39]	535108	1			T1	8		T3	444		T4	34
valid_sources[0x3a]	510526	1			T3	503		T4	25		T9	12
valid_sources[0x3b]	537201	1			T1	29		T3	522		T4	27
valid_sources[0x3c]	572333	1			T1	3		T3	452		T4	32
valid_sources[0x3d]	531903	1			T1	25		T3	520		T4	29
valid_sources[0x3e]	574462	1			T1	46		T3	484		T4	44
valid_sources[0x3f]	518816	1			T1	21		T3	518		T4	35
valid_sources[0x40]	632964	1			T1	31		T3	483		T4	22
valid_sources[0x41]	555820	1			T3	492		T4	37		T5	1
valid_sources[0x42]	546810	1			T1	13		T3	500		T4	32
valid_sources[0x43]	529210	1			T1	5		T3	443		T4	36
valid_sources[0x44]	572441	1			T1	46		T3	497		T4	43
valid_sources[0x45]	538623	1			T1	8		T3	524		T4	37
valid_sources[0x46]	599798	1			T1	10		T3	525		T4	35
valid_sources[0x47]	519912	1			T1	25		T3	501		T4	39
valid_sources[0x48]	576526	1			T1	28		T3	558		T4	29
valid_sources[0x49]	532000	1			T1	7		T3	483		T4	27
valid_sources[0x4a]	1545870	1			T1	12		T3	509		T4	39
valid_sources[0x4b]	581127	1			T1	14		T3	522		T4	30
valid_sources[0x4c]	527646	1			T1	25		T3	492		T4	34
valid_sources[0x4d]	580018	1			T1	37		T3	527		T4	37
valid_sources[0x4e]	516378	1			T1	28		T3	470		T4	37
valid_sources[0x4f]	528217	1			T1	15		T3	518		T4	36
valid_sources[0x50]	1619257	1			T1	29		T3	532		T4	29
valid_sources[0x51]	681631	1			T1	3		T3	493		T4	42
valid_sources[0x52]	564680	1			T1	6		T3	477		T4	34
valid_sources[0x53]	795260	1			T1	15		T3	547		T4	32
valid_sources[0x54]	562449	1			T1	2		T3	459		T4	33
valid_sources[0x55]	516482	1			T1	35		T3	507		T4	26
valid_sources[0x56]	529103	1			T1	9		T3	542		T4	41
valid_sources[0x57]	543193	1			T1	7		T3	533		T4	41
valid_sources[0x58]	514096	1			T1	8		T3	490		T4	31
valid_sources[0x59]	575316	1			T1	9		T3	468		T4	43
valid_sources[0x5a]	594703	1			T1	5		T3	509		T4	43
valid_sources[0x5b]	532844	1			T1	10		T3	447		T4	33
valid_sources[0x5c]	614379	1			T1	16		T3	543		T4	29
valid_sources[0x5d]	536613	1			T1	36		T3	519		T4	41
valid_sources[0x5e]	558598	1			T1	2		T3	467		T4	38
valid_sources[0x5f]	597679	1			T1	25		T3	456		T4	34
valid_sources[0x60]	550689	1			T1	12		T3	455		T4	35
valid_sources[0x61]	606549	1			T1	14		T3	489		T4	32
valid_sources[0x62]	561764	1			T1	15		T3	546		T4	39
valid_sources[0x63]	553826	1			T1	9		T3	502		T4	43
valid_sources[0x64]	1878029	1			T1	12		T3	526		T4	43
valid_sources[0x65]	624245	1			T1	15		T3	502		T4	40
valid_sources[0x66]	548995	1			T1	10		T3	567		T4	41
valid_sources[0x67]	616047	1			T1	29		T3	494		T4	24
valid_sources[0x68]	1265198	1			T1	6		T3	515		T4	29
valid_sources[0x69]	571950	1			T1	14		T3	560		T4	37
valid_sources[0x6a]	531439	1			T1	17		T3	502		T4	39
valid_sources[0x6b]	549480	1			T1	14		T3	483		T4	26
valid_sources[0x6c]	1648603	1			T1	2		T3	553		T4	39
valid_sources[0x6d]	538673	1			T1	29		T3	497		T4	29
valid_sources[0x6e]	520101	1			T1	41		T3	512		T4	36
valid_sources[0x6f]	528511	1			T3	539		T4	26		T5	41
valid_sources[0x70]	556352	1			T1	18		T3	516		T4	38
valid_sources[0x71]	539568	1			T1	21		T3	478		T4	45
valid_sources[0x72]	521326	1			T3	541		T4	30		T9	16
valid_sources[0x73]	548471	1			T1	21		T3	489		T4	29
valid_sources[0x74]	553723	1			T1	6		T3	489		T4	30
valid_sources[0x75]	572857	1			T1	10		T3	521		T4	31
valid_sources[0x76]	560902	1			T1	31		T3	476		T4	31
valid_sources[0x77]	553728	1			T1	19		T3	463		T4	35
valid_sources[0x78]	552914	1			T1	6		T3	513		T4	37
valid_sources[0x79]	603237	1			T1	17		T3	478		T4	34
valid_sources[0x7a]	553977	1			T1	17		T3	472		T4	33
valid_sources[0x7b]	512473	1			T1	7		T3	451		T4	37
valid_sources[0x7c]	791099	1			T1	24		T3	480		T4	42
valid_sources[0x7d]	516673	1			T1	13		T3	479		T4	35
valid_sources[0x7e]	561673	1			T1	12		T3	490		T4	41
valid_sources[0x7f]	535375	1			T1	7		T3	530		T4	28
valid_sources[0x80]	602422	1			T1	33		T3	514		T4	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

74295213

1

T1

444

T3

58362

T4

795

values[0x0]

all_enables

biggest_size

38529095

1

T1

254

T3

29421

T4

417

values[0x1]

all_enables

biggest_size

38535490

1

T1

229

T3

29208

T4

408

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34287	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149354

1

T3

9

T4

1

T5

26

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	53057	1			T5	28		T12	1030		T16	32
values[0x0]	63087	1			T2	1		T3	10		T5	22
values[0x1]	67497	1			T1	1		T3	17		T4	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25820	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

157821

1

T1

1

T3

11

T4

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	711	1			T12	10		T39	1		T29	1
valid_sources[0x01]	806	1			T12	8		T15	2		T7	1
valid_sources[0x02]	949	1			T4	2		T12	34		T23	1
valid_sources[0x03]	540	1			T12	2		T23	1		T16	5
valid_sources[0x04]	611	1			T5	1		T12	19		T15	4
valid_sources[0x05]	897	1			T12	36		T49	1		T28	7
valid_sources[0x06]	602	1			T12	42		T7	2		T28	7
valid_sources[0x07]	706	1			T12	20		T7	1		T28	1
valid_sources[0x08]	564	1			T12	4		T7	1		T28	11
valid_sources[0x09]	536	1			T12	17		T28	10		T41	1
valid_sources[0x0a]	690	1			T12	31		T23	1		T6	3
valid_sources[0x0b]	655	1			T12	20		T28	18		T29	125
valid_sources[0x0c]	532	1			T12	10		T28	2		T29	2
valid_sources[0x0d]	478	1			T12	18		T28	6		T125	2
valid_sources[0x0e]	487	1			T12	1		T15	2		T7	2
valid_sources[0x0f]	722	1			T12	7		T16	7		T28	4
valid_sources[0x10]	789	1			T12	19		T81	1		T28	3
valid_sources[0x11]	656	1			T12	13		T28	14		T29	15
valid_sources[0x12]	707	1			T2	1		T5	1		T12	2
valid_sources[0x13]	754	1			T12	40		T7	1		T28	13
valid_sources[0x14]	1031	1			T5	1		T12	20		T15	1
valid_sources[0x15]	512	1			T12	3		T28	10		T29	3
valid_sources[0x16]	690	1			T15	1		T6	4		T7	8
valid_sources[0x17]	621	1			T5	1		T8	1		T12	11
valid_sources[0x18]	798	1			T5	1		T12	28		T28	4
valid_sources[0x19]	598	1			T12	7		T28	1		T29	69
valid_sources[0x1a]	544	1			T12	1		T28	14		T126	2
valid_sources[0x1b]	880	1			T12	25		T29	2		T52	3
valid_sources[0x1c]	1094	1			T5	2		T12	1		T16	54
valid_sources[0x1d]	657	1			T5	1		T12	26		T39	1
valid_sources[0x1e]	768	1			T12	21		T28	1		T29	12
valid_sources[0x1f]	823	1			T5	1		T12	6		T28	2
valid_sources[0x20]	1227	1			T5	1		T12	11		T28	8
valid_sources[0x21]	808	1			T12	7		T28	15		T29	3
valid_sources[0x22]	516	1			T12	3		T42	1		T41	1
valid_sources[0x23]	593	1			T12	11		T7	1		T28	2
valid_sources[0x24]	1129	1			T5	2		T12	1		T7	5
valid_sources[0x25]	743	1			T12	20		T23	1		T39	1
valid_sources[0x26]	543	1			T12	15		T6	1		T7	1
valid_sources[0x27]	831	1			T12	7		T6	3		T7	1
valid_sources[0x28]	940	1			T12	8		T50	1		T39	1
valid_sources[0x29]	591	1			T12	23		T16	1		T28	9
valid_sources[0x2a]	522	1			T12	4		T23	1		T7	4
valid_sources[0x2b]	711	1			T12	15		T15	1		T6	1
valid_sources[0x2c]	588	1			T12	6		T39	1		T28	5
valid_sources[0x2d]	847	1			T12	37		T28	3		T29	141
valid_sources[0x2e]	763	1			T12	17		T7	5		T28	3
valid_sources[0x2f]	778	1			T12	5		T17	1		T39	1
valid_sources[0x30]	922	1			T12	32		T23	1		T24	9
valid_sources[0x31]	760	1			T5	4		T12	17		T24	22
valid_sources[0x32]	589	1			T12	10		T7	2		T50	3
valid_sources[0x33]	567	1			T12	30		T28	2		T42	1
valid_sources[0x34]	675	1			T12	14		T28	4		T29	83
valid_sources[0x35]	887	1			T12	28		T39	2		T28	3
valid_sources[0x36]	657	1			T12	33		T16	5		T7	1
valid_sources[0x37]	538	1			T12	7		T29	2		T53	3
valid_sources[0x38]	633	1			T12	4		T15	3		T7	1
valid_sources[0x39]	898	1			T12	19		T50	2		T28	2
valid_sources[0x3a]	584	1			T12	6		T7	3		T39	1
valid_sources[0x3b]	544	1			T12	25		T23	1		T6	2
valid_sources[0x3c]	771	1			T12	9		T6	1		T7	2
valid_sources[0x3d]	500	1			T12	7		T7	2		T28	12
valid_sources[0x3e]	1029	1			T12	15		T50	1		T82	9
valid_sources[0x3f]	593	1			T12	5		T7	2		T24	1
valid_sources[0x40]	909	1			T12	6		T39	1		T28	2
valid_sources[0x41]	540	1			T5	1		T12	16		T6	4
valid_sources[0x42]	596	1			T12	16		T24	2		T28	13
valid_sources[0x43]	640	1			T12	8		T7	1		T39	1
valid_sources[0x44]	522	1			T12	4		T28	17		T29	11
valid_sources[0x45]	863	1			T5	1		T12	22		T23	1
valid_sources[0x46]	785	1			T12	7		T15	3		T7	1
valid_sources[0x47]	663	1			T12	16		T28	1		T29	1
valid_sources[0x48]	658	1			T5	1		T12	19		T16	10
valid_sources[0x49]	658	1			T12	16		T24	3		T28	15
valid_sources[0x4a]	811	1			T23	1		T50	2		T28	2
valid_sources[0x4b]	551	1			T12	16		T7	1		T24	6
valid_sources[0x4c]	642	1			T12	30		T24	1		T50	5
valid_sources[0x4d]	716	1			T5	2		T12	9		T23	2
valid_sources[0x4e]	892	1			T12	27		T39	1		T28	12
valid_sources[0x4f]	982	1			T12	1		T28	7		T29	1
valid_sources[0x50]	1210	1			T12	13		T6	4		T28	5
valid_sources[0x51]	421	1			T12	5		T28	2		T42	14
valid_sources[0x52]	746	1			T5	1		T12	16		T80	4
valid_sources[0x53]	573	1			T12	3		T28	12		T29	1
valid_sources[0x54]	871	1			T12	15		T28	5		T41	2
valid_sources[0x55]	657	1			T28	16		T42	39		T40	3
valid_sources[0x56]	502	1			T11	1		T12	1		T24	1
valid_sources[0x57]	579	1			T12	21		T28	7		T29	99
valid_sources[0x58]	738	1			T12	16		T23	1		T7	1
valid_sources[0x59]	572	1			T12	14		T24	2		T28	10
valid_sources[0x5a]	503	1			T12	3		T28	3		T41	2
valid_sources[0x5b]	573	1			T12	30		T7	2		T28	4
valid_sources[0x5c]	739	1			T12	63		T28	4		T126	2
valid_sources[0x5d]	587	1			T10	16		T12	11		T28	1
valid_sources[0x5e]	662	1			T12	22		T16	3		T7	1
valid_sources[0x5f]	661	1			T12	5		T7	1		T50	2
valid_sources[0x60]	683	1			T12	2		T7	3		T50	3
valid_sources[0x61]	749	1			T12	2		T28	4		T29	2
valid_sources[0x62]	634	1			T12	32		T82	2		T29	1
valid_sources[0x63]	451	1			T23	1		T17	1		T7	1
valid_sources[0x64]	632	1			T5	1		T12	9		T17	1
valid_sources[0x65]	558	1			T12	2		T28	8		T42	20
valid_sources[0x66]	497	1			T5	4		T12	14		T28	1
valid_sources[0x67]	634	1			T12	7		T7	2		T28	3
valid_sources[0x68]	523	1			T12	9		T28	12		T29	1
valid_sources[0x69]	752	1			T12	13		T6	8		T7	2
valid_sources[0x6a]	874	1			T12	2		T7	6		T28	5
valid_sources[0x6b]	736	1			T9	1		T12	14		T6	5
valid_sources[0x6c]	699	1			T5	2		T12	4		T64	10
valid_sources[0x6d]	930	1			T5	2		T12	2		T28	5
valid_sources[0x6e]	721	1			T12	23		T15	2		T16	7
valid_sources[0x6f]	988	1			T12	3		T24	2		T28	12
valid_sources[0x70]	615	1			T12	3		T28	4		T29	12
valid_sources[0x71]	1014	1			T12	22		T7	9		T28	7
valid_sources[0x72]	631	1			T12	14		T7	2		T29	2
valid_sources[0x73]	551	1			T5	2		T12	1		T39	1
valid_sources[0x74]	611	1			T12	12		T28	8		T42	11
valid_sources[0x75]	846	1			T12	14		T49	1		T42	33
valid_sources[0x76]	502	1			T5	1		T12	7		T28	4
valid_sources[0x77]	575	1			T12	12		T16	5		T28	4
valid_sources[0x78]	628	1			T12	15		T15	2		T7	4
valid_sources[0x79]	841	1			T12	34		T13	5		T29	113
valid_sources[0x7a]	684	1			T12	19		T29	81		T52	2
valid_sources[0x7b]	634	1			T12	6		T28	9		T70	19
valid_sources[0x7c]	757	1			T5	1		T12	30		T28	4
valid_sources[0x7d]	524	1			T12	16		T24	9		T42	3
valid_sources[0x7e]	690	1			T12	20		T28	3		T29	61
valid_sources[0x7f]	836	1			T12	28		T28	2		T29	160
valid_sources[0x80]	626	1			T12	12		T7	2		T28	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40735

1

T5

19

T12

960

T16

14

values[0x0]

all_enables

biggest_size

55309

1

T3

4

T5

5

T10

1

values[0x1]

all_enables

biggest_size

53310

1

T3

5

T4

1

T5

2