Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16245069

1

T1

3782

T3

11507

T4

7217

full_word

148351911

1

T1

927

T3

116991

T4

1620

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	164596710	1			T1	4709		T3	128498		T4	8837
auto[TlIntgErrCmd]	76	1			T95	3		T96	1		T97	4
auto[TlIntgErrData]	102	1			T95	5		T96	5		T97	5
auto[TlIntgErrBoth]	92	1			T95	2		T96	4		T97	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

79326189

1

T1

2364

T3

64162

T4

4394

auto[1]

85270791

1

T1

2345

T3

64336

T4

4443

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7954699	1			T1	1920		T3	5800		T4	3599
auto[TlIntgErrNone]	partial	auto[1]	8290121	1			T1	1862		T3	5707		T4	3618
auto[TlIntgErrNone]	full_word	auto[0]	71371362	1			T1	444		T3	58362		T4	795
auto[TlIntgErrNone]	full_word	auto[1]	76980528	1			T1	483		T3	58629		T4	825
auto[TlIntgErrCmd]	partial	auto[0]	29	1			T95	2		T97	2		T106	1
auto[TlIntgErrCmd]	partial	auto[1]	42	1			T95	1		T96	1		T97	2
auto[TlIntgErrCmd]	full_word	auto[0]	1	1			T111	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T110	1		T107	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	52	1			T95	4		T96	3		T97	4
auto[TlIntgErrData]	partial	auto[1]	44	1			T95	1		T96	2		T97	1
auto[TlIntgErrData]	full_word	auto[0]	1	1			T113	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	5	1			T107	2		T114	2		T115	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1			T96	3		T97	1		T106	4
auto[TlIntgErrBoth]	partial	auto[1]	41	1			T95	2		T96	1		T106	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T110	1		T116	1		T109	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T113	1		T114	1		T111	1