Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	821519	1			T1	346		T4	1213		T5	20
auto[1]	10985893	1			T1	334		T3	30456		T4	1111
auto[2]	644011	1			T1	348		T4	1141		T5	20
auto[3]	10731191	1			T1	363		T3	30451		T4	903

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13675287	1			T1	25		T3	50538		T4	90
auto[1]	2240320	1			T1	150		T3	4907		T4	593
auto[2]	2268494	1			T1	184		T3	4969		T4	557
auto[3]	4998513	1			T1	1032		T3	493		T4	3128

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9228534

1

T1

1391

T3

60905

T4

4368

auto[1]

13954080

1

T3

2

T15

3

T16

2

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	372764	1			T1	8		T4	36		T5	15
auto[0]	auto[0]	auto[1]	38995	1			T1	51		T4	181		T5	5
auto[0]	auto[0]	auto[2]	38652	1			T1	49		T4	188		T82	617
auto[0]	auto[0]	auto[3]	72112	1			T1	238		T4	808		T82	64
auto[0]	auto[1]	auto[0]	3078046	1			T1	10		T3	25290		T4	7
auto[0]	auto[1]	auto[1]	336613	1			T1	52		T3	2432		T4	208
auto[0]	auto[1]	auto[2]	350766	1			T1	24		T3	2494		T4	27
auto[0]	auto[1]	auto[3]	496963	1			T1	248		T3	240		T4	869
auto[0]	auto[2]	auto[0]	275717	1			T1	2		T4	43		T5	16
auto[0]	auto[2]	auto[1]	33547	1			T1	34		T4	188		T5	2
auto[0]	auto[2]	auto[2]	27952	1			T1	50		T4	174		T5	2
auto[0]	auto[2]	auto[3]	52467	1			T1	262		T4	736		T82	69
auto[0]	auto[3]	auto[0]	2915636	1			T1	5		T3	25246		T4	4
auto[0]	auto[3]	auto[1]	330945	1			T1	13		T3	2475		T4	16
auto[0]	auto[3]	auto[2]	354743	1			T1	61		T3	2475		T4	168
auto[0]	auto[3]	auto[3]	452616	1			T1	284		T3	253		T4	715
auto[1]	auto[0]	auto[0]	9770	1			T40	1		T92	491		T120	1
auto[1]	auto[0]	auto[1]	44513	1			T92	2116		T119	1		T121	1762
auto[1]	auto[0]	auto[2]	44615	1			T92	2129		T121	1757		T122	1
auto[1]	auto[0]	auto[3]	200098	1			T68	3		T92	9316		T119	2
auto[1]	auto[1]	auto[0]	3509371	1			T15	3		T7	2		T49	60922
auto[1]	auto[1]	auto[1]	714658	1			T49	5275		T90	8768		T91	8222
auto[1]	auto[1]	auto[2]	706789	1			T49	6011		T90	8450		T91	9252
auto[1]	auto[1]	auto[3]	1792687	1			T49	541		T90	873		T91	37730
auto[1]	auto[2]	auto[0]	8706	1			T82	2		T92	446		T121	208
auto[1]	auto[2]	auto[1]	39415	1			T92	1994		T79	1		T118	2
auto[1]	auto[2]	auto[2]	37553	1			T41	1		T92	1545		T121	1892
auto[1]	auto[2]	auto[3]	168654	1			T92	6410		T121	8602		T123	22447
auto[1]	auto[3]	auto[0]	3505277	1			T3	2		T16	1		T49	61502
auto[1]	auto[3]	auto[1]	701634	1			T16	1		T49	5972		T90	8569
auto[1]	auto[3]	auto[2]	707424	1			T49	5407		T68	1		T90	8533
auto[1]	auto[3]	auto[3]	1762916	1			T49	527		T65	1		T90	859