Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1118869695	155971	0	0
ctrl_regwen_rd_A	1118869695	6491	0	0
exec_rd_A	1118869695	5949	0	0
exec_regwen_rd_A	1118869695	6351	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118869695	155971	0	0
T6	677735	0	0	0
T7	208106	0	0	0
T12	139057	3687	0	0
T13	190296	0	0	0
T14	147611	0	0	0
T15	147109	0	0	0
T16	616112	0	0	0
T17	1334	0	0	0
T23	115095	0	0	0
T28	0	1919	0	0
T29	0	9280	0	0
T42	0	2435	0	0
T43	0	1483	0	0
T44	0	4806	0	0
T45	0	2629	0	0
T46	0	3552	0	0
T47	0	2635	0	0
T48	0	4150	0	0
T49	338409	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118869695	6491	0	0
T18	785	0	0	0
T25	104383	0	0	0
T28	76069	343	0	0
T29	263295	0	0	0
T45	0	617	0	0
T47	0	327	0	0
T52	139996	0	0	0
T70	815852	0	0	0
T71	436322	0	0	0
T90	419622	0	0	0
T91	485283	0	0	0
T98	0	175	0	0
T99	0	1312	0	0
T100	0	639	0	0
T101	0	321	0	0
T102	0	531	0	0
T103	0	169	0	0
T104	0	73	0	0
T105	52698	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118869695	5949	0	0
T18	785	0	0	0
T25	104383	0	0	0
T28	76069	303	0	0
T29	263295	0	0	0
T45	0	565	0	0
T47	0	255	0	0
T52	139996	0	0	0
T70	815852	0	0	0
T71	436322	0	0	0
T90	419622	0	0	0
T91	485283	0	0	0
T98	0	148	0	0
T99	0	973	0	0
T100	0	544	0	0
T101	0	451	0	0
T102	0	501	0	0
T103	0	226	0	0
T104	0	82	0	0
T105	52698	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1118869695	6351	0	0
T18	785	0	0	0
T25	104383	0	0	0
T28	76069	338	0	0
T29	263295	0	0	0
T45	0	507	0	0
T47	0	345	0	0
T52	139996	0	0	0
T70	815852	0	0	0
T71	436322	0	0	0
T90	419622	0	0	0
T91	485283	0	0	0
T98	0	194	0	0
T99	0	1219	0	0
T100	0	612	0	0
T101	0	415	0	0
T102	0	460	0	0
T103	0	237	0	0
T104	0	103	0	0
T105	52698	0	0	0