Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	15624898	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

153714802

1

T1

4866

T2

2974

T3

6496

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	83307631	1			T1	2899		T2	31019		T3	4028
values[0x0]	41459407	1			T1	1373		T2	10050		T3	1815
values[0x1]	44572662	1			T1	1622		T2	21502		T3	2109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	7955741	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

161383959

1

T1

5385

T2

28125

T3

7268

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	623972	1			T1	28		T2	279		T3	41
valid_sources[0x01]	555374	1			T1	16		T2	222		T3	26
valid_sources[0x02]	599910	1			T1	20		T2	56		T3	15
valid_sources[0x03]	550913	1			T1	31		T2	32		T3	29
valid_sources[0x04]	536316	1			T1	22		T2	205		T3	35
valid_sources[0x05]	566714	1			T1	7		T2	220		T3	20
valid_sources[0x06]	601628	1			T1	24		T2	281		T3	39
valid_sources[0x07]	577088	1			T1	22		T2	253		T3	17
valid_sources[0x08]	531338	1			T1	18		T2	481		T3	37
valid_sources[0x09]	1723348	1			T1	28		T2	287		T3	36
valid_sources[0x0a]	519848	1			T1	15		T2	425		T3	31
valid_sources[0x0b]	554358	1			T1	21		T2	198		T3	20
valid_sources[0x0c]	515471	1			T1	28		T2	506		T3	32
valid_sources[0x0d]	537908	1			T1	20		T2	274		T3	41
valid_sources[0x0e]	521407	1			T1	33		T2	204		T3	39
valid_sources[0x0f]	530672	1			T1	21		T2	208		T3	21
valid_sources[0x10]	728747	1			T1	9		T2	208		T3	18
valid_sources[0x11]	595317	1			T1	13		T2	387		T3	34
valid_sources[0x12]	534587	1			T1	27		T2	286		T3	32
valid_sources[0x13]	521234	1			T1	24		T2	142		T3	17
valid_sources[0x14]	546543	1			T1	20		T2	82		T3	37
valid_sources[0x15]	549823	1			T1	25		T2	139		T3	27
valid_sources[0x16]	531678	1			T1	29		T2	118		T3	34
valid_sources[0x17]	522872	1			T1	29		T2	99		T3	31
valid_sources[0x18]	554560	1			T1	15		T2	248		T3	22
valid_sources[0x19]	551282	1			T1	21		T2	198		T3	29
valid_sources[0x1a]	569199	1			T1	27		T2	293		T3	34
valid_sources[0x1b]	618038	1			T1	36		T2	190		T3	31
valid_sources[0x1c]	583059	1			T1	25		T2	280		T3	31
valid_sources[0x1d]	555519	1			T1	6		T2	11		T3	34
valid_sources[0x1e]	518486	1			T1	31		T2	402		T3	29
valid_sources[0x1f]	529747	1			T1	42		T2	137		T3	21
valid_sources[0x20]	545782	1			T1	34		T2	293		T3	40
valid_sources[0x21]	1207401	1			T1	20		T2	115		T3	31
valid_sources[0x22]	545737	1			T1	30		T2	108		T3	22
valid_sources[0x23]	553783	1			T1	28		T2	274		T3	32
valid_sources[0x24]	572856	1			T1	24		T2	317		T3	55
valid_sources[0x25]	558398	1			T1	12		T2	180		T3	20
valid_sources[0x26]	533487	1			T1	15		T2	75		T3	30
valid_sources[0x27]	541603	1			T1	18		T2	529		T3	40
valid_sources[0x28]	551667	1			T1	30		T2	178		T3	48
valid_sources[0x29]	1308999	1			T1	21		T2	93		T3	32
valid_sources[0x2a]	565481	1			T1	25		T2	316		T3	29
valid_sources[0x2b]	563889	1			T1	17		T2	44		T3	30
valid_sources[0x2c]	662627	1			T1	38		T2	543		T3	22
valid_sources[0x2d]	572065	1			T1	22		T2	178		T3	42
valid_sources[0x2e]	1203953	1			T1	18		T2	340		T3	38
valid_sources[0x2f]	576078	1			T1	27		T2	129		T3	38
valid_sources[0x30]	540215	1			T1	10		T2	298		T3	36
valid_sources[0x31]	550260	1			T1	13		T2	214		T3	22
valid_sources[0x32]	555918	1			T1	25		T2	134		T3	23
valid_sources[0x33]	588454	1			T1	22		T2	378		T3	27
valid_sources[0x34]	557273	1			T1	28		T2	167		T3	35
valid_sources[0x35]	543689	1			T1	17		T2	123		T3	30
valid_sources[0x36]	563130	1			T1	10		T2	334		T3	43
valid_sources[0x37]	537432	1			T1	33		T2	303		T3	32
valid_sources[0x38]	546050	1			T1	20		T2	194		T3	32
valid_sources[0x39]	551126	1			T1	24		T2	662		T3	30
valid_sources[0x3a]	531713	1			T1	11		T2	10		T3	24
valid_sources[0x3b]	572662	1			T1	22		T2	147		T3	22
valid_sources[0x3c]	586064	1			T1	27		T2	424		T3	32
valid_sources[0x3d]	2070051	1			T1	22		T2	426		T3	39
valid_sources[0x3e]	526822	1			T1	37		T2	22		T3	26
valid_sources[0x3f]	531589	1			T1	31		T2	135		T3	37
valid_sources[0x40]	532717	1			T1	18		T2	179		T3	18
valid_sources[0x41]	523132	1			T1	16		T2	299		T3	37
valid_sources[0x42]	561874	1			T1	21		T2	505		T3	21
valid_sources[0x43]	567932	1			T1	45		T2	114		T3	34
valid_sources[0x44]	547804	1			T1	22		T2	198		T3	36
valid_sources[0x45]	538037	1			T1	20		T2	473		T3	36
valid_sources[0x46]	523307	1			T1	27		T2	496		T3	34
valid_sources[0x47]	548349	1			T1	36		T2	273		T3	49
valid_sources[0x48]	537935	1			T1	39		T2	381		T3	48
valid_sources[0x49]	647959	1			T1	6		T2	250		T3	25
valid_sources[0x4a]	535529	1			T1	27		T2	6		T3	29
valid_sources[0x4b]	589594	1			T1	22		T2	162		T3	32
valid_sources[0x4c]	546017	1			T1	7		T2	344		T3	38
valid_sources[0x4d]	560370	1			T1	14		T2	204		T3	50
valid_sources[0x4e]	516904	1			T1	32		T2	393		T3	34
valid_sources[0x4f]	558180	1			T1	14		T2	88		T3	23
valid_sources[0x50]	600989	1			T1	11		T2	49		T3	36
valid_sources[0x51]	518090	1			T1	12		T2	92		T3	33
valid_sources[0x52]	607451	1			T1	11		T2	120		T3	21
valid_sources[0x53]	543878	1			T1	13		T2	11		T3	35
valid_sources[0x54]	587522	1			T1	19		T2	62		T3	22
valid_sources[0x55]	566256	1			T1	19		T2	258		T3	38
valid_sources[0x56]	664312	1			T1	24		T2	177		T3	35
valid_sources[0x57]	537729	1			T1	22		T2	134		T3	37
valid_sources[0x58]	518469	1			T1	12		T2	620		T3	61
valid_sources[0x59]	543110	1			T1	25		T2	163		T3	45
valid_sources[0x5a]	558634	1			T1	26		T2	91		T3	33
valid_sources[0x5b]	559620	1			T1	33		T2	441		T3	36
valid_sources[0x5c]	525974	1			T1	35		T2	192		T3	28
valid_sources[0x5d]	518403	1			T1	20		T2	178		T3	16
valid_sources[0x5e]	647956	1			T1	31		T2	18		T3	32
valid_sources[0x5f]	3046846	1			T1	21		T2	157		T3	34
valid_sources[0x60]	585105	1			T1	33		T2	114		T3	24
valid_sources[0x61]	970910	1			T1	38		T2	268		T3	31
valid_sources[0x62]	567857	1			T1	16		T2	344		T3	34
valid_sources[0x63]	570464	1			T1	14		T2	440		T3	22
valid_sources[0x64]	567430	1			T1	22		T2	408		T3	31
valid_sources[0x65]	520592	1			T1	33		T2	317		T3	32
valid_sources[0x66]	1732572	1			T1	12		T2	282		T3	30
valid_sources[0x67]	527184	1			T1	11		T2	98		T3	39
valid_sources[0x68]	540351	1			T1	35		T2	486		T3	24
valid_sources[0x69]	520375	1			T1	13		T2	322		T3	50
valid_sources[0x6a]	576454	1			T1	15		T2	130		T3	43
valid_sources[0x6b]	539772	1			T1	21		T2	293		T3	28
valid_sources[0x6c]	1181579	1			T1	19		T2	74		T3	51
valid_sources[0x6d]	535381	1			T1	18		T2	86		T3	53
valid_sources[0x6e]	612696	1			T1	27		T2	413		T3	26
valid_sources[0x6f]	517958	1			T1	12		T2	176		T3	30
valid_sources[0x70]	718120	1			T1	20		T2	188		T3	27
valid_sources[0x71]	518977	1			T1	17		T2	387		T3	24
valid_sources[0x72]	566625	1			T1	33		T2	65		T3	26
valid_sources[0x73]	543677	1			T1	22		T2	414		T3	20
valid_sources[0x74]	580343	1			T1	23		T2	220		T3	25
valid_sources[0x75]	1800352	1			T1	6		T2	300		T3	41
valid_sources[0x76]	583026	1			T1	19		T2	120		T3	35
valid_sources[0x77]	543853	1			T1	21		T2	329		T3	34
valid_sources[0x78]	594049	1			T1	35		T2	162		T3	25
valid_sources[0x79]	558856	1			T1	28		T2	84		T3	22
valid_sources[0x7a]	565039	1			T1	18		T2	725		T3	33
valid_sources[0x7b]	553159	1			T1	20		T2	217		T3	25
valid_sources[0x7c]	534018	1			T1	25		T2	152		T3	52
valid_sources[0x7d]	586334	1			T1	20		T2	290		T3	45
valid_sources[0x7e]	550311	1			T1	28		T2	729		T3	37
valid_sources[0x7f]	548508	1			T1	38		T2	123		T3	13
valid_sources[0x80]	519535	1			T1	17		T2	570		T3	31

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

75452668

1

T1

2373

T2

258

T3

3299

values[0x0]

all_enables

biggest_size

39128826

1

T1

1226

T2

1372

T3

1603

values[0x1]

all_enables

biggest_size

39133308

1

T1

1267

T2

1344

T3

1594

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	33619	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

149722

1

T10

1

T4

10

T12

40

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	52925	1			T4	10		T12	24		T7	37
values[0x0]	63005	1			T3	2		T10	3		T4	19
values[0x1]	67411	1			T1	2		T2	1		T10	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	25292	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

158049

1

T10

2

T4

15

T12

51

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	652	1			T9	8		T28	1		T29	1
valid_sources[0x01]	585	1			T12	1		T31	9		T32	5
valid_sources[0x02]	600	1			T28	1		T31	5		T54	1
valid_sources[0x03]	696	1			T12	2		T40	2		T29	1
valid_sources[0x04]	612	1			T10	1		T12	2		T143	1
valid_sources[0x05]	800	1			T41	2		T28	1		T20	2
valid_sources[0x06]	912	1			T6	1		T144	12		T145	2
valid_sources[0x07]	561	1			T6	1		T8	4		T9	1
valid_sources[0x08]	543	1			T28	1		T31	7		T120	1
valid_sources[0x09]	640	1			T12	1		T8	4		T9	5
valid_sources[0x0a]	668	1			T12	1		T40	2		T29	1
valid_sources[0x0b]	772	1			T28	1		T31	3		T32	18
valid_sources[0x0c]	889	1			T146	4		T28	1		T31	9
valid_sources[0x0d]	660	1			T12	1		T63	2		T23	2
valid_sources[0x0e]	475	1			T12	3		T63	7		T40	1
valid_sources[0x0f]	589	1			T12	3		T9	1		T40	2
valid_sources[0x10]	782	1			T12	1		T6	1		T19	1
valid_sources[0x11]	967	1			T12	1		T8	1		T29	1
valid_sources[0x12]	758	1			T12	1		T28	1		T31	9
valid_sources[0x13]	683	1			T28	1		T31	10		T32	19
valid_sources[0x14]	651	1			T145	1		T31	13		T54	2
valid_sources[0x15]	761	1			T12	1		T145	1		T31	6
valid_sources[0x16]	683	1			T12	1		T40	2		T31	6
valid_sources[0x17]	594	1			T28	1		T31	2		T32	11
valid_sources[0x18]	950	1			T9	1		T40	1		T43	2
valid_sources[0x19]	554	1			T46	1		T9	1		T38	3
valid_sources[0x1a]	568	1			T29	1		T31	7		T120	2
valid_sources[0x1b]	840	1			T28	1		T29	3		T31	9
valid_sources[0x1c]	575	1			T12	1		T23	1		T40	1
valid_sources[0x1d]	696	1			T12	1		T9	3		T23	1
valid_sources[0x1e]	895	1			T12	2		T6	1		T27	3
valid_sources[0x1f]	710	1			T10	1		T6	1		T40	1
valid_sources[0x20]	838	1			T9	1		T31	12		T120	1
valid_sources[0x21]	616	1			T28	2		T31	11		T54	1
valid_sources[0x22]	577	1			T12	1		T40	1		T31	4
valid_sources[0x23]	744	1			T12	1		T31	7		T32	13
valid_sources[0x24]	666	1			T29	1		T31	18		T120	1
valid_sources[0x25]	563	1			T6	1		T8	3		T23	1
valid_sources[0x26]	681	1			T9	2		T27	5		T31	3
valid_sources[0x27]	941	1			T9	4		T29	1		T31	2
valid_sources[0x28]	765	1			T46	4		T27	2		T28	2
valid_sources[0x29]	767	1			T23	2		T40	1		T28	1
valid_sources[0x2a]	1066	1			T23	2		T38	1		T31	6
valid_sources[0x2b]	875	1			T12	1		T31	10		T120	2
valid_sources[0x2c]	627	1			T9	2		T27	1		T40	1
valid_sources[0x2d]	661	1			T13	1		T9	1		T27	2
valid_sources[0x2e]	607	1			T31	11		T54	1		T120	1
valid_sources[0x2f]	814	1			T9	1		T40	2		T20	1
valid_sources[0x30]	643	1			T6	1		T145	1		T31	4
valid_sources[0x31]	968	1			T38	2		T28	1		T31	11
valid_sources[0x32]	674	1			T12	1		T9	4		T45	1
valid_sources[0x33]	533	1			T63	2		T31	12		T54	1
valid_sources[0x34]	572	1			T12	1		T6	1		T8	3
valid_sources[0x35]	851	1			T10	1		T12	2		T143	1
valid_sources[0x36]	693	1			T6	1		T31	5		T32	18
valid_sources[0x37]	673	1			T1	2		T12	1		T31	6
valid_sources[0x38]	520	1			T147	1		T29	2		T31	6
valid_sources[0x39]	567	1			T145	2		T29	1		T31	9
valid_sources[0x3a]	598	1			T3	2		T40	1		T28	1
valid_sources[0x3b]	847	1			T12	1		T40	2		T31	13
valid_sources[0x3c]	668	1			T13	3		T23	1		T40	1
valid_sources[0x3d]	661	1			T13	1		T16	1		T40	1
valid_sources[0x3e]	575	1			T12	1		T23	1		T38	1
valid_sources[0x3f]	589	1			T12	2		T9	8		T40	1
valid_sources[0x40]	1006	1			T12	1		T5	1		T9	9
valid_sources[0x41]	600	1			T10	1		T19	1		T40	1
valid_sources[0x42]	1016	1			T6	1		T9	3		T40	1
valid_sources[0x43]	691	1			T8	4		T9	7		T27	1
valid_sources[0x44]	638	1			T9	6		T148	8		T38	1
valid_sources[0x45]	1064	1			T6	2		T149	1		T23	1
valid_sources[0x46]	608	1			T10	1		T13	1		T28	1
valid_sources[0x47]	636	1			T105	18		T97	3		T31	7
valid_sources[0x48]	647	1			T40	1		T31	9		T32	6
valid_sources[0x49]	799	1			T145	2		T29	1		T31	5
valid_sources[0x4a]	737	1			T13	5		T9	4		T31	8
valid_sources[0x4b]	526	1			T12	1		T6	1		T40	2
valid_sources[0x4c]	778	1			T9	1		T145	2		T31	12
valid_sources[0x4d]	766	1			T12	2		T6	1		T8	4
valid_sources[0x4e]	679	1			T40	1		T31	5		T32	9
valid_sources[0x4f]	804	1			T6	1		T9	1		T40	4
valid_sources[0x50]	524	1			T9	4		T28	1		T31	11
valid_sources[0x51]	704	1			T12	1		T6	2		T23	1
valid_sources[0x52]	649	1			T12	1		T6	1		T150	2
valid_sources[0x53]	500	1			T151	1		T31	9		T32	4
valid_sources[0x54]	762	1			T12	1		T9	1		T40	2
valid_sources[0x55]	920	1			T12	1		T8	5		T28	2
valid_sources[0x56]	530	1			T45	1		T20	2		T31	8
valid_sources[0x57]	483	1			T152	1		T145	1		T31	5
valid_sources[0x58]	727	1			T9	6		T63	1		T31	13
valid_sources[0x59]	538	1			T145	1		T29	1		T31	10
valid_sources[0x5a]	903	1			T12	1		T9	1		T42	1
valid_sources[0x5b]	559	1			T38	1		T29	1		T31	11
valid_sources[0x5c]	698	1			T75	1		T9	1		T31	6
valid_sources[0x5d]	612	1			T63	9		T40	3		T42	1
valid_sources[0x5e]	589	1			T12	1		T27	2		T40	1
valid_sources[0x5f]	625	1			T40	1		T28	3		T145	2
valid_sources[0x60]	732	1			T12	1		T40	1		T152	2
valid_sources[0x61]	803	1			T12	1		T27	1		T31	5
valid_sources[0x62]	1130	1			T6	1		T19	1		T23	1
valid_sources[0x63]	570	1			T12	2		T28	1		T31	7
valid_sources[0x64]	729	1			T12	1		T9	5		T40	1
valid_sources[0x65]	597	1			T9	1		T31	11		T32	20
valid_sources[0x66]	724	1			T13	1		T153	2		T152	1
valid_sources[0x67]	459	1			T12	1		T31	11		T120	1
valid_sources[0x68]	595	1			T4	49		T9	3		T63	1
valid_sources[0x69]	540	1			T9	9		T28	2		T29	1
valid_sources[0x6a]	923	1			T9	1		T151	1		T31	9
valid_sources[0x6b]	553	1			T31	8		T32	18		T154	1
valid_sources[0x6c]	669	1			T8	4		T31	9		T120	3
valid_sources[0x6d]	889	1			T8	1		T146	2		T23	2
valid_sources[0x6e]	631	1			T6	1		T19	2		T27	4
valid_sources[0x6f]	679	1			T63	5		T40	1		T28	1
valid_sources[0x70]	772	1			T27	1		T31	16		T120	1
valid_sources[0x71]	751	1			T12	2		T40	2		T31	10
valid_sources[0x72]	596	1			T12	1		T28	1		T29	1
valid_sources[0x73]	898	1			T12	1		T9	5		T155	1
valid_sources[0x74]	504	1			T29	1		T31	4		T32	18
valid_sources[0x75]	582	1			T6	1		T63	1		T31	7
valid_sources[0x76]	591	1			T15	17		T28	1		T29	1
valid_sources[0x77]	635	1			T6	2		T31	3		T120	2
valid_sources[0x78]	872	1			T40	1		T42	1		T31	8
valid_sources[0x79]	535	1			T28	2		T31	8		T54	1
valid_sources[0x7a]	885	1			T40	2		T28	1		T145	2
valid_sources[0x7b]	720	1			T12	1		T8	2		T27	3
valid_sources[0x7c]	1001	1			T40	1		T29	1		T31	8
valid_sources[0x7d]	558	1			T40	1		T31	7		T32	6
valid_sources[0x7e]	628	1			T12	1		T19	2		T156	1
valid_sources[0x7f]	1149	1			T8	2		T28	1		T29	1
valid_sources[0x80]	1166	1			T12	1		T40	3		T31	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40624

1

T4

3

T12

15

T7

18

values[0x0]

all_enables

biggest_size

55481

1

T10

1

T4

5

T12

17

values[0x1]

all_enables

biggest_size

53617

1

T4

2

T12

8

T13

2