Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15561993

1

T1

1028

T2

59597

T3

1456

full_word

150900519

1

T1

4866

T2

2974

T3

6496

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	166462242	1			T1	5894		T2	62571		T3	7952
auto[TlIntgErrCmd]	93	1			T102	2		T103	8		T104	4
auto[TlIntgErrData]	84	1			T102	3		T103	1		T104	1
auto[TlIntgErrBoth]	93	1			T102	5		T103	11		T104	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

80354655

1

T1

2899

T2

31019

T3

4028

auto[1]

86107857

1

T1

2995

T2

31552

T3

3924

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7626563	1			T1	526		T2	30761		T3	729
auto[TlIntgErrNone]	partial	auto[1]	7935182	1			T1	502		T2	28836		T3	727
auto[TlIntgErrNone]	full_word	auto[0]	72727967	1			T1	2373		T2	258		T3	3299
auto[TlIntgErrNone]	full_word	auto[1]	78172530	1			T1	2493		T2	2716		T3	3197
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T102	2		T103	2		T104	4
auto[TlIntgErrCmd]	partial	auto[1]	47	1			T103	6		T121	1		T122	4
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T123	1		T125	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T128	1		T124	1		T127	1
auto[TlIntgErrData]	partial	auto[0]	41	1			T102	2		T103	1		T104	1
auto[TlIntgErrData]	partial	auto[1]	33	1			T102	1		T128	2		T129	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T121	1		T122	1		T130	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T131	1		T132	1		T127	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1			T102	1		T103	1		T104	3
auto[TlIntgErrBoth]	partial	auto[1]	53	1			T102	4		T103	8		T104	2
auto[TlIntgErrBoth]	full_word	auto[0]	2	1			T130	1		T133	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	3	1			T103	2		T124	1		-	-