| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 66.67 | 1 | 100 | 1 | 1 | 64 | 64 |
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.scr_key_rotated.success | 0.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_sram_ctrl_regs_reg_block.exec.en | 100.00 | 1 | 100 | 1 | 64 | 64 |
| mubi4_cov_of_mubi4_cov_of_tb.dut.u_hw_debug_en_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 0.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 6 | 0 | 0.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 6 | 0 | 0.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
| 100.00 | 1 | 100 | 1 | 64 | 64 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Variables | 6 | 0 | 6 | 100.00 |
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 6 | 0 | 0.00 |
| NAME | COUNT | AT LEAST | NUMBER | STATUS |
| others[0] | 0 | 1 | 1 | |
| others[1] | 0 | 1 | 1 | |
| others[2] | 0 | 1 | 1 | |
| others[3] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 | |
| true | 0 | 1 | 1 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 106 | 1 | T12 | 1 | T7 | 1 | T63 | 1 | ||||
| others[1] | 95 | 1 | T12 | 1 | T7 | 2 | T38 | 1 | ||||
| others[2] | 93 | 1 | T12 | 1 | T15 | 1 | T8 | 1 | ||||
| others[3] | 147 | 1 | T12 | 2 | T7 | 1 | T8 | 1 | ||||
| false | 931 | 1 | T4 | 4 | T12 | 11 | T7 | 6 | ||||
| true | 863 | 1 | T4 | 6 | T12 | 8 | T7 | 6 |
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins | 6 | 0 | 6 | 100.00 |
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 87 | 1 | T12 | 1 | T7 | 1 | T9 | 1 | ||||
| others[1] | 630 | 1 | T4 | 2 | T12 | 7 | T7 | 3 | ||||
| others[2] | 5973 | 1 | T1 | 1 | T2 | 1 | T3 | 1 | ||||
| others[3] | 150 | 1 | T4 | 2 | T46 | 1 | T15 | 1 | ||||
| false | 33 | 1 | T9 | 1 | T38 | 1 | T40 | 1 | ||||
| true | 34 | 1 | T8 | 1 | T63 | 1 | T135 | 1 |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |