Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	789249	1			T4	2554		T15	1879		T16	750
auto[1]	10052864	1			T1	2899		T2	29644		T3	4027
auto[2]	617440	1			T4	1340		T15	904		T16	364
auto[3]	9819073	1			T1	2994		T2	30056		T3	3923

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13255539	1			T1	4069		T2	240		T3	5274
auto[1]	1941836	1			T1	796		T2	2723		T3	1220
auto[2]	1979541	1			T1	837		T2	5117		T3	1175
auto[3]	4101710	1			T1	191		T2	51620		T3	281

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9443136

1

T1

5893

T2

59698

T3

7950

auto[1]

11835490

1

T2

2

T10

165470

T13

4

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	321888	1			T4	2150		T15	1522		T16	624
auto[0]	auto[0]	auto[1]	33376	1			T4	188		T15	175		T16	55
auto[0]	auto[0]	auto[2]	33509	1			T4	196		T15	170		T16	66
auto[0]	auto[0]	auto[3]	73855	1			T4	20		T15	12		T16	5
auto[0]	auto[1]	auto[0]	3116297	1			T1	1986		T2	24		T3	2663
auto[0]	auto[1]	auto[1]	338051	1			T1	387		T2	223		T3	635
auto[0]	auto[1]	auto[2]	361685	1			T1	428		T2	2718		T3	590
auto[0]	auto[1]	auto[3]	593757	1			T1	98		T2	26677		T3	139
auto[0]	auto[2]	auto[0]	238217	1			T4	1137		T15	734		T16	306
auto[0]	auto[2]	auto[1]	29593	1			T4	90		T15	97		T16	36
auto[0]	auto[2]	auto[2]	22717	1			T4	103		T15	66		T16	19
auto[0]	auto[2]	auto[3]	51852	1			T4	10		T15	7		T16	3
auto[0]	auto[3]	auto[0]	2980897	1			T1	2083		T2	216		T3	2611
auto[0]	auto[3]	auto[1]	344518	1			T1	409		T2	2500		T3	585
auto[0]	auto[3]	auto[2]	362947	1			T1	409		T2	2399		T3	585
auto[0]	auto[3]	auto[3]	539977	1			T1	93		T2	24941		T3	142
auto[1]	auto[0]	auto[0]	10735	1			T97	295		T139	2		T140	840
auto[1]	auto[0]	auto[1]	48837	1			T97	1425		T140	3895		T141	2975
auto[1]	auto[0]	auto[2]	48654	1			T97	1343		T140	3882		T141	3014
auto[1]	auto[0]	auto[3]	218395	1			T97	6435		T62	2		T138	3
auto[1]	auto[1]	auto[0]	3291281	1			T10	2698		T13	2		T6	1
auto[1]	auto[1]	auto[1]	576522	1			T10	12257		T95	7086		T96	6523
auto[1]	auto[1]	auto[2]	539304	1			T10	12375		T95	6970		T9	1
auto[1]	auto[1]	auto[3]	1235967	1			T2	2		T10	55313		T95	694
auto[1]	auto[2]	auto[0]	9085	1			T97	181		T140	814		T141	648
auto[1]	auto[2]	auto[1]	40284	1			T97	854		T140	3642		T141	2668
auto[1]	auto[2]	auto[2]	41018	1			T97	1567		T140	2598		T141	1971
auto[1]	auto[2]	auto[3]	184674	1			T97	6942		T62	1		T140	11510
auto[1]	auto[3]	auto[0]	3287139	1			T10	2709		T13	2		T6	1
auto[1]	auto[3]	auto[1]	530655	1			T10	12227		T95	6905		T96	7061
auto[1]	auto[3]	auto[2]	569707	1			T10	12198		T6	1		T8	1
auto[1]	auto[3]	auto[3]	1203233	1			T10	55693		T95	635		T96	609