Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1139916518	146211	0	0
ctrl_regwen_rd_A	1139916518	8096	0	0
exec_rd_A	1139916518	7167	0	0
exec_regwen_rd_A	1139916518	8063	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139916518	146211	0	0
T31	116787	2320	0	0
T32	0	2404	0	0
T33	0	1711	0	0
T47	0	2776	0	0
T48	0	1293	0	0
T49	0	3399	0	0
T50	0	2117	0	0
T51	0	2232	0	0
T52	0	996	0	0
T53	0	6412	0	0
T54	770126	0	0	0
T55	915426	0	0	0
T56	415977	0	0	0
T57	73187	0	0	0
T58	33634	0	0	0
T59	686230	0	0	0
T60	236257	0	0	0
T61	393868	0	0	0
T62	261714	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139916518	8096	0	0
T21	935	0	0	0
T33	53128	299	0	0
T48	0	332	0	0
T50	0	493	0	0
T51	0	381	0	0
T52	0	256	0	0
T106	0	617	0	0
T107	0	485	0	0
T108	0	299	0	0
T109	0	121	0	0
T110	0	180	0	0
T111	75713	0	0	0
T112	283702	0	0	0
T113	178974	0	0	0
T114	103541	0	0	0
T115	756323	0	0	0
T116	61685	0	0	0
T117	503476	0	0	0
T118	163071	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139916518	7167	0	0
T21	935	0	0	0
T33	53128	189	0	0
T48	0	266	0	0
T50	0	234	0	0
T51	0	405	0	0
T52	0	204	0	0
T106	0	562	0	0
T107	0	562	0	0
T108	0	253	0	0
T109	0	184	0	0
T110	0	164	0	0
T111	75713	0	0	0
T112	283702	0	0	0
T113	178974	0	0	0
T114	103541	0	0	0
T115	756323	0	0	0
T116	61685	0	0	0
T117	503476	0	0	0
T118	163071	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1139916518	8063	0	0
T21	935	0	0	0
T33	53128	269	0	0
T48	0	311	0	0
T50	0	404	0	0
T51	0	359	0	0
T52	0	337	0	0
T106	0	664	0	0
T107	0	508	0	0
T108	0	306	0	0
T109	0	135	0	0
T110	0	135	0	0
T111	75713	0	0	0
T112	283702	0	0	0
T113	178974	0	0	0
T114	103541	0	0	0
T115	756323	0	0	0
T116	61685	0	0	0
T117	503476	0	0	0
T118	163071	0	0	0