Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16319017	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

144445935

1

T1

196606

T2

3429

T3

144179

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	79126810	1			T1	65536		T2	1833		T3	720896
values[0x0]	39194964	1			T1	65880		T2	916		T3	360305
values[0x1]	42443178	1			T1	65190		T2	1035		T3	360591

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8300145	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

152464807

1

T1

196606

T2

3601

T3

144179

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	523477	1			T2	19		T3	5678		T4	12
valid_sources[0x01]	519125	1			T2	4		T3	5636		T4	5
valid_sources[0x02]	536421	1			T2	7		T3	5653		T4	12
valid_sources[0x03]	539609	1			T2	7		T3	5664		T4	13
valid_sources[0x04]	530786	1			T2	8		T3	5633		T4	13
valid_sources[0x05]	546138	1			T2	22		T3	5658		T4	14
valid_sources[0x06]	832491	1			T2	22		T3	5740		T4	11
valid_sources[0x07]	727037	1			T2	10		T3	5499		T4	13
valid_sources[0x08]	531343	1			T2	27		T3	5815		T4	11
valid_sources[0x09]	528970	1			T2	9		T3	5537		T4	11
valid_sources[0x0a]	519505	1			T2	9		T3	5589		T4	10
valid_sources[0x0b]	543794	1			T2	30		T3	5642		T4	11
valid_sources[0x0c]	556759	1			T2	14		T3	5567		T4	16
valid_sources[0x0d]	567464	1			T2	13		T3	5677		T4	9
valid_sources[0x0e]	572674	1			T2	8		T3	5596		T4	16
valid_sources[0x0f]	554599	1			T2	18		T3	5677		T4	13
valid_sources[0x10]	595912	1			T2	4		T3	5654		T4	15
valid_sources[0x11]	917886	1			T2	6		T3	5602		T4	12
valid_sources[0x12]	636471	1			T2	3		T3	5656		T4	10
valid_sources[0x13]	1890267	1			T2	11		T3	5601		T4	16
valid_sources[0x14]	557240	1			T2	19		T3	5650		T4	17
valid_sources[0x15]	607062	1			T2	21		T3	5485		T4	14
valid_sources[0x16]	528158	1			T2	22		T3	5670		T4	8
valid_sources[0x17]	994703	1			T2	17		T3	5677		T4	10
valid_sources[0x18]	559470	1			T2	17		T3	5467		T4	9
valid_sources[0x19]	543442	1			T2	13		T3	5649		T4	5
valid_sources[0x1a]	608179	1			T2	23		T3	5657		T4	9
valid_sources[0x1b]	522999	1			T2	4		T3	5764		T4	8
valid_sources[0x1c]	554529	1			T2	18		T3	5663		T4	16
valid_sources[0x1d]	531317	1			T2	11		T3	5660		T4	6
valid_sources[0x1e]	521238	1			T2	16		T3	5687		T4	9
valid_sources[0x1f]	551214	1			T2	11		T3	5666		T4	11
valid_sources[0x20]	918049	1			T2	9		T3	5630		T4	18
valid_sources[0x21]	529958	1			T2	24		T3	5611		T4	11
valid_sources[0x22]	608410	1			T2	8		T3	5632		T4	16
valid_sources[0x23]	534560	1			T2	24		T3	5613		T4	10
valid_sources[0x24]	576528	1			T2	7		T3	5660		T4	7
valid_sources[0x25]	532747	1			T2	14		T3	5680		T4	14
valid_sources[0x26]	544821	1			T2	10		T3	5695		T4	17
valid_sources[0x27]	551553	1			T2	14		T3	5705		T4	12
valid_sources[0x28]	544134	1			T2	13		T3	5617		T4	13
valid_sources[0x29]	548902	1			T2	4		T3	5640		T4	9
valid_sources[0x2a]	532824	1			T2	24		T3	5575		T4	9
valid_sources[0x2b]	530423	1			T2	13		T3	5619		T4	13
valid_sources[0x2c]	547093	1			T2	13		T3	5703		T4	12
valid_sources[0x2d]	556778	1			T2	14		T3	5635		T4	15
valid_sources[0x2e]	543988	1			T2	14		T3	5582		T4	10
valid_sources[0x2f]	526115	1			T2	27		T3	5644		T4	16
valid_sources[0x30]	557605	1			T2	22		T3	5684		T4	15
valid_sources[0x31]	536953	1			T2	7		T3	5753		T4	12
valid_sources[0x32]	553813	1			T2	3		T3	5630		T4	16
valid_sources[0x33]	613515	1			T2	13		T3	5688		T4	8
valid_sources[0x34]	526597	1			T2	11		T3	5557		T4	13
valid_sources[0x35]	594553	1			T2	22		T3	5680		T4	6
valid_sources[0x36]	553064	1			T2	12		T3	5501		T4	10
valid_sources[0x37]	559934	1			T2	22		T3	5649		T4	7
valid_sources[0x38]	532877	1			T2	16		T3	5672		T4	7
valid_sources[0x39]	564864	1			T2	20		T3	5659		T4	11
valid_sources[0x3a]	521441	1			T2	19		T3	5660		T4	10
valid_sources[0x3b]	574503	1			T2	14		T3	5533		T4	12
valid_sources[0x3c]	569042	1			T2	17		T3	5745		T4	12
valid_sources[0x3d]	735950	1			T2	18		T3	5680		T4	13
valid_sources[0x3e]	2008642	1			T2	32		T3	5647		T4	17
valid_sources[0x3f]	566123	1			T2	17		T3	5596		T4	12
valid_sources[0x40]	573312	1			T2	22		T3	5575		T4	12
valid_sources[0x41]	533220	1			T2	10		T3	5653		T4	9
valid_sources[0x42]	540886	1			T2	18		T3	5509		T4	9
valid_sources[0x43]	563035	1			T2	28		T3	5613		T4	12
valid_sources[0x44]	550901	1			T2	19		T3	5646		T4	12
valid_sources[0x45]	543240	1			T2	22		T3	5649		T4	8
valid_sources[0x46]	550215	1			T2	19		T3	5789		T4	4
valid_sources[0x47]	549488	1			T2	13		T3	5663		T4	16
valid_sources[0x48]	1309901	1			T2	9		T3	5567		T4	7
valid_sources[0x49]	575880	1			T2	18		T3	5673		T4	15
valid_sources[0x4a]	540997	1			T2	8		T3	5638		T4	14
valid_sources[0x4b]	555377	1			T2	6		T3	5822		T4	12
valid_sources[0x4c]	545279	1			T2	16		T3	5587		T4	8
valid_sources[0x4d]	529689	1			T2	19		T3	5630		T4	11
valid_sources[0x4e]	533777	1			T2	28		T3	5591		T4	12
valid_sources[0x4f]	1020418	1			T2	11		T3	5785		T4	14
valid_sources[0x50]	659846	1			T2	19		T3	5616		T4	8
valid_sources[0x51]	575221	1			T2	13		T3	5631		T4	7
valid_sources[0x52]	564632	1			T2	32		T3	5723		T4	9
valid_sources[0x53]	591221	1			T2	33		T3	5595		T4	8
valid_sources[0x54]	532101	1			T2	9		T3	5684		T4	8
valid_sources[0x55]	564990	1			T2	3		T3	5695		T4	11
valid_sources[0x56]	552299	1			T2	23		T3	5701		T4	10
valid_sources[0x57]	568259	1			T2	9		T3	5636		T4	10
valid_sources[0x58]	526862	1			T2	25		T3	5457		T4	8
valid_sources[0x59]	580281	1			T2	14		T3	5604		T4	9
valid_sources[0x5a]	516194	1			T2	5		T3	5621		T4	14
valid_sources[0x5b]	527973	1			T2	6		T3	5688		T4	11
valid_sources[0x5c]	549964	1			T2	8		T3	5565		T4	9
valid_sources[0x5d]	1277911	1			T2	20		T3	5657		T4	6
valid_sources[0x5e]	536788	1			T2	21		T3	5642		T4	13
valid_sources[0x5f]	561457	1			T2	5		T3	5651		T4	7
valid_sources[0x60]	549481	1			T2	18		T3	5725		T4	10
valid_sources[0x61]	558973	1			T2	14		T3	5712		T4	13
valid_sources[0x62]	541171	1			T2	10		T3	5670		T4	11
valid_sources[0x63]	1736237	1			T2	10		T3	5629		T4	10
valid_sources[0x64]	591866	1			T2	3		T3	5601		T4	9
valid_sources[0x65]	1573578	1			T2	7		T3	5535		T4	11
valid_sources[0x66]	539127	1			T2	16		T3	5664		T4	9
valid_sources[0x67]	533464	1			T2	14		T3	5688		T4	12
valid_sources[0x68]	1711585	1			T2	14		T3	5683		T4	11
valid_sources[0x69]	525463	1			T2	13		T3	5624		T4	14
valid_sources[0x6a]	553293	1			T2	5		T3	5714		T4	7
valid_sources[0x6b]	542312	1			T2	14		T3	5691		T4	9
valid_sources[0x6c]	757383	1			T2	8		T3	5691		T4	14
valid_sources[0x6d]	535607	1			T2	20		T3	5590		T4	7
valid_sources[0x6e]	576112	1			T2	19		T3	5723		T4	9
valid_sources[0x6f]	551480	1			T2	20		T3	5677		T4	8
valid_sources[0x70]	541644	1			T2	4		T3	5536		T4	6
valid_sources[0x71]	517656	1			T2	26		T3	5616		T4	7
valid_sources[0x72]	519896	1			T2	14		T3	5535		T4	9
valid_sources[0x73]	530989	1			T2	12		T3	5611		T4	8
valid_sources[0x74]	522608	1			T2	11		T3	5505		T4	19
valid_sources[0x75]	551522	1			T2	7		T3	5550		T4	8
valid_sources[0x76]	559376	1			T2	11		T3	5700		T4	6
valid_sources[0x77]	548847	1			T2	24		T3	5655		T4	10
valid_sources[0x78]	528901	1			T2	16		T3	5580		T4	6
valid_sources[0x79]	565451	1			T2	8		T3	5604		T4	13
valid_sources[0x7a]	554102	1			T2	10		T3	5659		T4	13
valid_sources[0x7b]	556325	1			T2	12		T3	5541		T4	9
valid_sources[0x7c]	560073	1			T2	8		T3	5673		T4	11
valid_sources[0x7d]	540223	1			T2	12		T3	5606		T4	10
valid_sources[0x7e]	557391	1			T2	24		T3	5674		T4	10
valid_sources[0x7f]	559480	1			T2	15		T3	5460		T4	13
valid_sources[0x80]	559302	1			T2	18		T3	5514		T4	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

70925071

1

T1

65536

T2

1665

T3

720896

values[0x0]

all_enables

biggest_size

36757824

1

T1

65880

T2

855

T3

360305

values[0x1]

all_enables

biggest_size

36763040

1

T1

65190

T2

909

T3

360591

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	32406	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156647

1

T2

21

T3

7

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54545	1			T2	32		T15	17		T17	14
values[0x0]	64817	1			T2	20		T3	11		T4	1
values[0x1]	69691	1			T2	11		T3	11		T4	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	24260	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164793

1

T2

25

T3

10

T5

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	704	1			T15	1		T19	7		T8	1
valid_sources[0x01]	931	1			T19	9		T8	1		T28	65
valid_sources[0x02]	1031	1			T19	10		T8	3		T9	1
valid_sources[0x03]	1030	1			T15	1		T19	8		T28	47
valid_sources[0x04]	793	1			T19	18		T28	52		T119	1
valid_sources[0x05]	658	1			T19	15		T28	18		T99	2
valid_sources[0x06]	594	1			T19	13		T28	38		T125	1
valid_sources[0x07]	988	1			T19	24		T28	12		T126	8
valid_sources[0x08]	814	1			T19	21		T8	2		T28	21
valid_sources[0x09]	639	1			T19	14		T28	30		T26	2
valid_sources[0x0a]	646	1			T19	14		T8	1		T28	15
valid_sources[0x0b]	808	1			T19	13		T28	40		T26	1
valid_sources[0x0c]	819	1			T19	5		T8	1		T28	12
valid_sources[0x0d]	858	1			T19	17		T8	1		T28	29
valid_sources[0x0e]	652	1			T19	10		T28	28		T26	1
valid_sources[0x0f]	1010	1			T19	19		T28	29		T127	2
valid_sources[0x10]	746	1			T15	1		T19	14		T28	39
valid_sources[0x11]	748	1			T19	10		T28	9		T26	3
valid_sources[0x12]	573	1			T19	18		T28	22		T41	5
valid_sources[0x13]	626	1			T19	14		T8	1		T28	40
valid_sources[0x14]	544	1			T19	8		T28	33		T128	1
valid_sources[0x15]	789	1			T15	2		T19	12		T8	1
valid_sources[0x16]	562	1			T19	3		T28	21		T99	3
valid_sources[0x17]	622	1			T3	1		T19	21		T28	15
valid_sources[0x18]	916	1			T19	9		T28	90		T27	1
valid_sources[0x19]	716	1			T19	14		T8	1		T28	21
valid_sources[0x1a]	793	1			T15	1		T19	13		T28	20
valid_sources[0x1b]	818	1			T15	1		T19	15		T28	16
valid_sources[0x1c]	570	1			T15	3		T19	18		T28	28
valid_sources[0x1d]	628	1			T19	13		T8	1		T28	2
valid_sources[0x1e]	643	1			T19	20		T8	2		T28	50
valid_sources[0x1f]	596	1			T19	13		T8	1		T28	19
valid_sources[0x20]	659	1			T15	1		T19	17		T8	2
valid_sources[0x21]	812	1			T15	1		T19	8		T8	2
valid_sources[0x22]	738	1			T19	10		T28	62		T49	3
valid_sources[0x23]	667	1			T19	8		T8	1		T28	2
valid_sources[0x24]	953	1			T14	1		T19	7		T28	53
valid_sources[0x25]	768	1			T19	6		T9	2		T28	41
valid_sources[0x26]	791	1			T15	2		T19	3		T11	80
valid_sources[0x27]	924	1			T4	2		T19	19		T35	2
valid_sources[0x28]	668	1			T19	5		T8	2		T28	6
valid_sources[0x29]	764	1			T19	13		T8	1		T28	48
valid_sources[0x2a]	797	1			T19	4		T9	2		T28	8
valid_sources[0x2b]	1198	1			T15	1		T19	15		T8	1
valid_sources[0x2c]	692	1			T19	6		T8	3		T28	19
valid_sources[0x2d]	698	1			T19	7		T8	1		T28	7
valid_sources[0x2e]	501	1			T19	15		T28	8		T29	1
valid_sources[0x2f]	636	1			T19	6		T28	28		T30	1
valid_sources[0x30]	590	1			T19	13		T38	1		T28	8
valid_sources[0x31]	685	1			T19	13		T28	21		T21	8
valid_sources[0x32]	919	1			T19	25		T8	1		T9	1
valid_sources[0x33]	698	1			T15	1		T19	17		T28	12
valid_sources[0x34]	802	1			T15	2		T19	11		T28	19
valid_sources[0x35]	681	1			T19	12		T28	30		T27	5
valid_sources[0x36]	1009	1			T14	1		T15	2		T19	12
valid_sources[0x37]	577	1			T15	4		T19	7		T8	1
valid_sources[0x38]	1184	1			T19	17		T28	48		T29	103
valid_sources[0x39]	740	1			T14	1		T19	21		T8	1
valid_sources[0x3a]	540	1			T19	27		T28	13		T27	1
valid_sources[0x3b]	655	1			T19	16		T28	6		T27	2
valid_sources[0x3c]	922	1			T7	11		T19	7		T8	2
valid_sources[0x3d]	566	1			T19	16		T28	21		T26	1
valid_sources[0x3e]	975	1			T15	1		T19	22		T8	3
valid_sources[0x3f]	743	1			T19	23		T28	17		T119	1
valid_sources[0x40]	774	1			T19	14		T8	2		T28	6
valid_sources[0x41]	511	1			T19	8		T28	3		T41	5
valid_sources[0x42]	629	1			T19	10		T28	12		T41	7
valid_sources[0x43]	572	1			T19	14		T8	2		T119	2
valid_sources[0x44]	771	1			T19	14		T8	2		T28	40
valid_sources[0x45]	686	1			T19	16		T8	1		T28	11
valid_sources[0x46]	852	1			T15	1		T19	16		T9	1
valid_sources[0x47]	801	1			T2	63		T19	12		T28	5
valid_sources[0x48]	1066	1			T15	1		T19	11		T28	12
valid_sources[0x49]	820	1			T19	13		T8	1		T28	40
valid_sources[0x4a]	795	1			T15	1		T19	14		T28	10
valid_sources[0x4b]	617	1			T15	1		T19	7		T24	2
valid_sources[0x4c]	706	1			T3	2		T19	7		T8	1
valid_sources[0x4d]	831	1			T15	3		T19	26		T9	1
valid_sources[0x4e]	658	1			T19	16		T28	8		T120	1
valid_sources[0x4f]	852	1			T15	1		T18	2		T19	14
valid_sources[0x50]	710	1			T19	5		T8	6		T28	9
valid_sources[0x51]	707	1			T19	17		T28	32		T49	1
valid_sources[0x52]	601	1			T19	15		T8	2		T28	50
valid_sources[0x53]	608	1			T19	6		T8	2		T28	13
valid_sources[0x54]	639	1			T19	18		T28	55		T27	2
valid_sources[0x55]	657	1			T19	6		T8	1		T28	19
valid_sources[0x56]	619	1			T19	28		T8	1		T28	23
valid_sources[0x57]	582	1			T15	2		T19	24		T28	11
valid_sources[0x58]	687	1			T19	16		T8	1		T28	6
valid_sources[0x59]	754	1			T15	2		T19	26		T28	9
valid_sources[0x5a]	650	1			T19	16		T28	23		T26	1
valid_sources[0x5b]	847	1			T17	70		T19	10		T8	1
valid_sources[0x5c]	692	1			T15	3		T19	9		T28	15
valid_sources[0x5d]	840	1			T19	10		T8	2		T28	2
valid_sources[0x5e]	767	1			T19	15		T28	17		T129	2
valid_sources[0x5f]	636	1			T19	19		T28	50		T26	2
valid_sources[0x60]	593	1			T19	12		T8	1		T28	15
valid_sources[0x61]	606	1			T18	1		T19	15		T9	1
valid_sources[0x62]	805	1			T19	22		T8	2		T28	4
valid_sources[0x63]	880	1			T19	8		T28	18		T27	1
valid_sources[0x64]	749	1			T15	3		T19	14		T28	30
valid_sources[0x65]	692	1			T15	1		T19	20		T8	1
valid_sources[0x66]	669	1			T14	1		T15	1		T19	8
valid_sources[0x67]	675	1			T19	6		T8	1		T28	21
valid_sources[0x68]	792	1			T19	7		T8	2		T28	69
valid_sources[0x69]	689	1			T15	1		T19	9		T8	1
valid_sources[0x6a]	666	1			T19	21		T28	23		T22	1
valid_sources[0x6b]	761	1			T19	6		T8	1		T9	1
valid_sources[0x6c]	1020	1			T19	18		T8	1		T28	22
valid_sources[0x6d]	835	1			T19	19		T28	23		T26	1
valid_sources[0x6e]	810	1			T15	1		T19	6		T28	37
valid_sources[0x6f]	582	1			T19	5		T28	3		T99	1
valid_sources[0x70]	691	1			T19	12		T28	23		T27	2
valid_sources[0x71]	597	1			T19	12		T28	46		T24	3
valid_sources[0x72]	901	1			T15	2		T19	8		T8	1
valid_sources[0x73]	859	1			T19	15		T8	1		T28	7
valid_sources[0x74]	589	1			T15	2		T19	5		T28	32
valid_sources[0x75]	611	1			T19	16		T28	1		T24	2
valid_sources[0x76]	662	1			T14	4		T15	1		T19	9
valid_sources[0x77]	586	1			T19	13		T8	2		T28	54
valid_sources[0x78]	652	1			T19	16		T8	1		T28	43
valid_sources[0x79]	685	1			T12	5		T19	14		T37	2
valid_sources[0x7a]	748	1			T19	26		T28	4		T41	1
valid_sources[0x7b]	777	1			T19	10		T8	1		T28	28
valid_sources[0x7c]	642	1			T19	11		T9	1		T28	15
valid_sources[0x7d]	615	1			T19	11		T28	19		T60	4
valid_sources[0x7e]	819	1			T14	2		T19	11		T28	52
valid_sources[0x7f]	637	1			T15	2		T19	9		T28	16
valid_sources[0x80]	1069	1			T6	1		T19	5		T8	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

42708

1

T2

14

T15

9

T17

8

values[0x0]

all_enables

biggest_size

57517

1

T2

7

T3

5

T7

2

values[0x1]

all_enables

biggest_size

56422

1

T3

2

T5

1

T7

2