Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16285553

1

T2

125

T4

254

T5

436

full_word

141795305

1

T1

196606

T2

1196

T3

144179

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	158080568	1			T1	196606		T2	1321		T3	144179
auto[TlIntgErrCmd]	84	1			T100	7		T101	2		T102	3
auto[TlIntgErrData]	87	1			T100	6		T101	3		T102	9
auto[TlIntgErrBoth]	119	1			T100	7		T101	5		T102	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76348073

1

T1

65536

T2

635

T3

720896

auto[1]

81732785

1

T1

131070

T2

686

T3

720896

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7991344	1			T2	63		T4	130		T5	211
auto[TlIntgErrNone]	partial	auto[1]	8293948	1			T2	62		T4	124		T5	225
auto[TlIntgErrNone]	full_word	auto[0]	68356599	1			T1	65536		T2	572		T3	720896
auto[TlIntgErrNone]	full_word	auto[1]	73438677	1			T1	131070		T2	624		T3	720896
auto[TlIntgErrCmd]	partial	auto[0]	31	1			T100	3		T101	1		T108	3
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T100	3		T101	1		T102	3
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T100	1		T110	1		T113	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T108	1		T110	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	35	1			T100	1		T101	1		T102	4
auto[TlIntgErrData]	partial	auto[1]	47	1			T100	5		T101	2		T102	5
auto[TlIntgErrData]	full_word	auto[0]	2	1			T113	1		T111	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	3	1			T113	2		T114	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	50	1			T100	5		T101	2		T102	3
auto[TlIntgErrBoth]	partial	auto[1]	57	1			T100	2		T101	2		T102	3
auto[TlIntgErrBoth]	full_word	auto[0]	6	1			T110	1		T112	1		T113	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T101	1		T102	2		T112	1