Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	933784	1			T6	8342		T7	12254		T15	3431
auto[1]	10965215	1			T2	566		T5	1145		T6	7661
auto[2]	742738	1			T6	5639		T7	10961		T15	1995
auto[3]	10690326	1			T2	633		T5	1161		T6	5243

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13942097	1			T2	1000		T5	1521		T6	10
auto[1]	2207839	1			T2	93		T5	349		T6	876
auto[2]	2231291	1			T2	99		T5	350		T6	727
auto[3]	4950836	1			T2	7		T5	86		T6	25272

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9645164

1

T2

1199

T5

2306

T6

26882

auto[1]

13686899

1

T6

3

T15

1

T18

117342

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	389166	1			T7	10140		T15	2822		T17	1818
auto[0]	auto[0]	auto[1]	40279	1			T6	78		T7	1050		T15	285
auto[0]	auto[0]	auto[2]	40425	1			T6	71		T7	968		T15	293
auto[0]	auto[0]	auto[3]	123424	1			T6	8190		T7	96		T15	30
auto[0]	auto[1]	auto[0]	3133562	1			T2	476		T5	764		T6	1
auto[0]	auto[1]	auto[1]	343458	1			T2	35		T5	170		T6	59
auto[0]	auto[1]	auto[2]	360203	1			T2	50		T5	171		T6	123
auto[0]	auto[1]	auto[3]	564261	1			T2	5		T5	40		T6	7478
auto[0]	auto[2]	auto[0]	308320	1			T6	4		T7	9275		T15	1648
auto[0]	auto[2]	auto[1]	40407	1			T6	678		T7	950		T15	154
auto[0]	auto[2]	auto[2]	28756	1			T6	47		T7	675		T15	173
auto[0]	auto[2]	auto[3]	85656	1			T6	4910		T7	61		T15	20
auto[0]	auto[3]	auto[0]	2982343	1			T2	524		T5	757		T6	5
auto[0]	auto[3]	auto[1]	338664	1			T2	58		T5	179		T6	61
auto[0]	auto[3]	auto[2]	363301	1			T2	49		T5	179		T6	486
auto[0]	auto[3]	auto[3]	502939	1			T2	2		T5	46		T6	4691
auto[1]	auto[0]	auto[0]	11033	1			T15	1		T86	725		T88	753
auto[1]	auto[0]	auto[1]	50671	1			T86	3170		T88	3520		T90	2289
auto[1]	auto[0]	auto[2]	50442	1			T86	3174		T88	3490		T90	2273
auto[1]	auto[0]	auto[3]	228344	1			T6	3		T40	4		T86	14675
auto[1]	auto[1]	auto[0]	3554840	1			T18	48474		T39	81627		T21	1
auto[1]	auto[1]	auto[1]	688956	1			T18	4388		T39	6963		T85	8208
auto[1]	auto[1]	auto[2]	667182	1			T18	4960		T39	8110		T85	8410
auto[1]	auto[1]	auto[3]	1652753	1			T18	441		T39	723		T40	1
auto[1]	auto[2]	auto[0]	9962	1			T86	646		T88	724		T90	305
auto[1]	auto[2]	auto[1]	44904	1			T86	2980		T88	3268		T90	1371
auto[1]	auto[2]	auto[2]	40712	1			T86	2690		T88	2313		T90	2479
auto[1]	auto[2]	auto[3]	184021	1			T40	1		T86	12505		T88	10388
auto[1]	auto[3]	auto[0]	3552871	1			T18	49041		T39	81162		T21	1
auto[1]	auto[3]	auto[1]	660500	1			T18	4979		T39	8028		T85	8259
auto[1]	auto[3]	auto[2]	680270	1			T18	4540		T39	7207		T85	8215
auto[1]	auto[3]	auto[3]	1609438	1			T18	519		T39	696		T40	1