Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1152133756	147647	0	0
ctrl_regwen_rd_A	1152133756	11328	0	0
exec_rd_A	1152133756	9837	0	0
exec_regwen_rd_A	1152133756	11466	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152133756	147647	0	0
T8	281198	0	0	0
T9	481918	0	0	0
T10	27291	0	0	0
T11	22811	0	0	0
T19	116864	2699	0	0
T20	168464	0	0	0
T28	0	5888	0	0
T29	0	6714	0	0
T35	66744	0	0	0
T36	75847	0	0	0
T37	76866	0	0	0
T38	242847	0	0	0
T41	0	2045	0	0
T42	0	3249	0	0
T43	0	2762	0	0
T44	0	1202	0	0
T45	0	4778	0	0
T46	0	939	0	0
T47	0	933	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152133756	11328	0	0
T8	281198	0	0	0
T9	481918	0	0	0
T10	27291	0	0	0
T11	22811	0	0	0
T19	116864	350	0	0
T20	168464	0	0	0
T35	66744	0	0	0
T36	75847	0	0	0
T37	76866	0	0	0
T38	242847	0	0	0
T42	0	812	0	0
T43	0	388	0	0
T44	0	156	0	0
T47	0	99	0	0
T103	0	180	0	0
T104	0	874	0	0
T105	0	70	0	0
T106	0	673	0	0
T107	0	126	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152133756	9837	0	0
T8	281198	0	0	0
T9	481918	0	0	0
T10	27291	0	0	0
T11	22811	0	0	0
T19	116864	342	0	0
T20	168464	0	0	0
T35	66744	0	0	0
T36	75847	0	0	0
T37	76866	0	0	0
T38	242847	0	0	0
T42	0	660	0	0
T43	0	386	0	0
T44	0	126	0	0
T47	0	101	0	0
T103	0	93	0	0
T104	0	708	0	0
T105	0	37	0	0
T106	0	552	0	0
T107	0	76	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1152133756	11466	0	0
T8	281198	0	0	0
T9	481918	0	0	0
T10	27291	0	0	0
T11	22811	0	0	0
T19	116864	409	0	0
T20	168464	0	0	0
T35	66744	0	0	0
T36	75847	0	0	0
T37	76866	0	0	0
T38	242847	0	0	0
T42	0	880	0	0
T43	0	376	0	0
T44	0	171	0	0
T47	0	89	0	0
T103	0	192	0	0
T104	0	861	0	0
T105	0	101	0	0
T106	0	678	0	0
T107	0	152	0	0