Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16218917	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

156630524

1

T1

664084

T2

230241

T5

3191

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85162848	1			T1	339267		T2	126830		T5	1546
values[0x0]	42233068	1			T1	168295		T2	60762		T5	787
values[0x1]	45453525	1			T1	170682		T2	65820		T5	858

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8249180	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

164600261

1

T1

671228

T2

241875

T5

3191

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	640414	1			T1	2702		T2	932		T5	9
valid_sources[0x01]	653060	1			T1	2702		T2	972		T5	7
valid_sources[0x02]	524188	1			T1	2728		T2	1063		T5	18
valid_sources[0x03]	545426	1			T1	2663		T2	805		T5	6
valid_sources[0x04]	645488	1			T1	2677		T2	897		T5	15
valid_sources[0x05]	550749	1			T1	2615		T2	941		T5	20
valid_sources[0x06]	521051	1			T1	2601		T2	886		T5	23
valid_sources[0x07]	653578	1			T1	2642		T2	1074		T5	18
valid_sources[0x08]	543673	1			T1	2624		T2	1096		T5	18
valid_sources[0x09]	571656	1			T1	2686		T2	990		T5	7
valid_sources[0x0a]	543121	1			T1	2754		T2	908		T9	6483
valid_sources[0x0b]	551794	1			T1	2648		T2	941		T5	13
valid_sources[0x0c]	545034	1			T1	2704		T2	1007		T5	7
valid_sources[0x0d]	566651	1			T1	2655		T2	1080		T5	17
valid_sources[0x0e]	611131	1			T1	2551		T2	1128		T5	11
valid_sources[0x0f]	552476	1			T1	2650		T2	1063		T5	16
valid_sources[0x10]	545762	1			T1	2576		T2	971		T5	31
valid_sources[0x11]	548667	1			T1	2655		T2	963		T5	16
valid_sources[0x12]	609691	1			T1	2696		T2	1124		T5	18
valid_sources[0x13]	530055	1			T1	2713		T2	1001		T5	10
valid_sources[0x14]	544022	1			T1	2725		T2	1003		T5	11
valid_sources[0x15]	527841	1			T1	2803		T2	864		T5	10
valid_sources[0x16]	1290000	1			T1	2489		T2	894		T5	5
valid_sources[0x17]	552021	1			T1	2744		T2	1067		T5	6
valid_sources[0x18]	583428	1			T1	2580		T2	902		T5	23
valid_sources[0x19]	2071227	1			T1	2642		T2	1025		T5	5
valid_sources[0x1a]	630517	1			T1	2588		T2	911		T5	3
valid_sources[0x1b]	532503	1			T1	2691		T2	881		T5	18
valid_sources[0x1c]	591277	1			T1	2587		T2	1076		T5	3
valid_sources[0x1d]	546263	1			T1	2537		T2	1036		T5	16
valid_sources[0x1e]	549100	1			T1	2674		T2	1167		T5	16
valid_sources[0x1f]	533329	1			T1	2822		T2	1004		T5	14
valid_sources[0x20]	593707	1			T1	2464		T2	1136		T5	6
valid_sources[0x21]	774383	1			T1	2690		T2	979		T5	7
valid_sources[0x22]	522856	1			T1	2557		T2	918		T5	21
valid_sources[0x23]	538818	1			T1	2892		T2	988		T5	20
valid_sources[0x24]	744540	1			T1	2692		T2	1012		T5	24
valid_sources[0x25]	566998	1			T1	2596		T2	1059		T5	17
valid_sources[0x26]	2106180	1			T1	2740		T2	963		T5	17
valid_sources[0x27]	664305	1			T1	2652		T2	953		T5	10
valid_sources[0x28]	521956	1			T1	2541		T2	964		T5	22
valid_sources[0x29]	535650	1			T1	2742		T2	999		T5	14
valid_sources[0x2a]	526260	1			T1	2547		T2	920		T5	13
valid_sources[0x2b]	547854	1			T1	2589		T2	1152		T5	18
valid_sources[0x2c]	549257	1			T1	2696		T2	1083		T5	23
valid_sources[0x2d]	543027	1			T1	2543		T2	943		T5	17
valid_sources[0x2e]	582617	1			T1	2497		T2	956		T5	15
valid_sources[0x2f]	588641	1			T1	2769		T2	852		T5	4
valid_sources[0x30]	590422	1			T1	2763		T2	976		T5	13
valid_sources[0x31]	555564	1			T1	2710		T2	1048		T5	8
valid_sources[0x32]	527257	1			T1	2796		T2	1014		T5	10
valid_sources[0x33]	564625	1			T1	2764		T2	996		T5	13
valid_sources[0x34]	574600	1			T1	2630		T2	1030		T5	19
valid_sources[0x35]	723523	1			T1	2602		T2	1042		T5	20
valid_sources[0x36]	564676	1			T1	2592		T2	964		T5	27
valid_sources[0x37]	558287	1			T1	2741		T2	1021		T5	25
valid_sources[0x38]	520132	1			T1	2831		T2	965		T5	6
valid_sources[0x39]	555758	1			T1	2670		T2	1160		T5	9
valid_sources[0x3a]	559539	1			T1	2534		T2	1088		T5	24
valid_sources[0x3b]	648670	1			T1	2772		T2	900		T5	15
valid_sources[0x3c]	2131780	1			T1	2576		T2	960		T5	15
valid_sources[0x3d]	562009	1			T1	2743		T2	886		T5	20
valid_sources[0x3e]	541858	1			T1	2505		T2	1077		T5	29
valid_sources[0x3f]	537601	1			T1	2783		T2	1059		T5	12
valid_sources[0x40]	592994	1			T1	2677		T2	1083		T5	17
valid_sources[0x41]	527784	1			T1	2698		T2	912		T5	10
valid_sources[0x42]	605664	1			T1	2661		T2	1108		T5	3
valid_sources[0x43]	558611	1			T1	2646		T2	1159		T5	15
valid_sources[0x44]	549168	1			T1	2519		T2	1003		T5	9
valid_sources[0x45]	586915	1			T1	2675		T2	945		T5	3
valid_sources[0x46]	549220	1			T1	2769		T2	1040		T5	10
valid_sources[0x47]	553878	1			T1	2550		T2	1042		T5	5
valid_sources[0x48]	534334	1			T1	2546		T2	987		T5	6
valid_sources[0x49]	637513	1			T1	2627		T2	958		T5	4
valid_sources[0x4a]	519498	1			T1	2759		T2	1068		T5	5
valid_sources[0x4b]	563782	1			T1	2761		T2	1043		T5	13
valid_sources[0x4c]	557148	1			T1	2643		T2	1061		T5	19
valid_sources[0x4d]	544758	1			T1	2694		T2	913		T5	1
valid_sources[0x4e]	738714	1			T1	2492		T2	840		T5	20
valid_sources[0x4f]	572313	1			T1	2782		T2	963		T5	3
valid_sources[0x50]	639181	1			T1	2797		T2	976		T5	21
valid_sources[0x51]	689471	1			T1	2561		T2	894		T5	3
valid_sources[0x52]	592184	1			T1	2626		T2	997		T5	7
valid_sources[0x53]	536329	1			T1	2610		T2	928		T5	13
valid_sources[0x54]	533765	1			T1	2596		T2	992		T5	7
valid_sources[0x55]	524381	1			T1	2669		T2	1112		T5	7
valid_sources[0x56]	530347	1			T1	2518		T2	992		T5	20
valid_sources[0x57]	606978	1			T1	2566		T2	1071		T5	12
valid_sources[0x58]	562151	1			T1	2690		T2	948		T5	6
valid_sources[0x59]	548611	1			T1	2691		T2	1003		T5	15
valid_sources[0x5a]	588602	1			T1	2553		T2	956		T5	19
valid_sources[0x5b]	2039836	1			T1	2721		T2	871		T5	8
valid_sources[0x5c]	587536	1			T1	2522		T2	1022		T5	2
valid_sources[0x5d]	549165	1			T1	2657		T2	1025		T5	18
valid_sources[0x5e]	591165	1			T1	2537		T2	971		T5	4
valid_sources[0x5f]	1027604	1			T1	2750		T2	884		T5	3
valid_sources[0x60]	607290	1			T1	2661		T2	929		T5	13
valid_sources[0x61]	560630	1			T1	2701		T2	857		T5	21
valid_sources[0x62]	522586	1			T1	2513		T2	959		T5	2
valid_sources[0x63]	604730	1			T1	2519		T2	990		T5	11
valid_sources[0x64]	3400096	1			T1	2658		T2	755		T5	10
valid_sources[0x65]	561781	1			T1	2582		T2	980		T5	7
valid_sources[0x66]	535898	1			T1	2709		T2	955		T5	10
valid_sources[0x67]	535451	1			T1	2700		T2	945		T5	3
valid_sources[0x68]	549115	1			T1	2527		T2	1018		T5	4
valid_sources[0x69]	581407	1			T1	2534		T2	1140		T5	10
valid_sources[0x6a]	614419	1			T1	2548		T2	1031		T5	12
valid_sources[0x6b]	560375	1			T1	2600		T2	921		T5	20
valid_sources[0x6c]	551099	1			T1	2638		T2	772		T5	5
valid_sources[0x6d]	641834	1			T1	2596		T2	1065		T5	41
valid_sources[0x6e]	566034	1			T1	2752		T2	1022		T5	9
valid_sources[0x6f]	557361	1			T1	2621		T2	944		T5	5
valid_sources[0x70]	561994	1			T1	2518		T2	1086		T5	7
valid_sources[0x71]	1623304	1			T1	2563		T2	1098		T5	11
valid_sources[0x72]	617105	1			T1	2659		T2	1113		T5	3
valid_sources[0x73]	1625078	1			T1	2538		T2	1085		T5	3
valid_sources[0x74]	571452	1			T1	2685		T2	801		T5	17
valid_sources[0x75]	551191	1			T1	2579		T2	1018		T5	10
valid_sources[0x76]	562785	1			T1	2755		T2	1015		T5	9
valid_sources[0x77]	534774	1			T1	2664		T2	783		T5	1
valid_sources[0x78]	2313269	1			T1	2645		T2	998		T5	16
valid_sources[0x79]	595188	1			T1	2510		T2	1074		T5	20
valid_sources[0x7a]	613639	1			T1	2520		T2	946		T5	6
valid_sources[0x7b]	554273	1			T1	2615		T2	989		T5	15
valid_sources[0x7c]	527036	1			T1	2711		T2	1024		T5	3
valid_sources[0x7d]	544934	1			T1	2597		T2	811		T5	6
valid_sources[0x7e]	626094	1			T1	2569		T2	971		T5	7
valid_sources[0x7f]	642454	1			T1	2657		T2	1151		T5	13
valid_sources[0x80]	662840	1			T1	2603		T2	869		T5	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77011351

1

T1

332083

T2

115333

T5

1546

values[0x0]

all_enables

biggest_size

39814719

1

T1

166217

T2

57263

T5

787

values[0x1]

all_enables

biggest_size

39804454

1

T1

165784

T2

57645

T5

858

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35973	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

148058

1

T1

54

T9

7

T11

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	54206	1			T1	50		T30	1149		T28	669
values[0x0]	62585	1			T1	44		T2	1		T5	2
values[0x1]	67240	1			T1	55		T2	4		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	27138	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

156893

1

T1

64

T3

1

T9

11

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	769	1			T1	1		T18	1		T30	3
valid_sources[0x01]	614	1			T1	1		T30	43		T28	11
valid_sources[0x02]	569	1			T19	1		T30	7		T28	12
valid_sources[0x03]	595	1			T1	1		T30	24		T28	10
valid_sources[0x04]	529	1			T1	1		T30	8		T28	8
valid_sources[0x05]	613	1			T1	1		T30	4		T28	10
valid_sources[0x06]	442	1			T30	4		T28	9		T8	1
valid_sources[0x07]	922	1			T1	2		T30	13		T28	10
valid_sources[0x08]	781	1			T1	1		T30	31		T28	15
valid_sources[0x09]	754	1			T30	35		T28	12		T31	1
valid_sources[0x0a]	693	1			T1	4		T30	8		T28	13
valid_sources[0x0b]	659	1			T1	1		T30	22		T28	7
valid_sources[0x0c]	699	1			T1	1		T30	16		T28	8
valid_sources[0x0d]	979	1			T1	3		T30	14		T28	11
valid_sources[0x0e]	1306	1			T19	1		T30	8		T28	8
valid_sources[0x0f]	650	1			T30	46		T28	10		T55	1
valid_sources[0x10]	695	1			T30	1		T28	9		T8	1
valid_sources[0x11]	724	1			T1	1		T4	2		T19	1
valid_sources[0x12]	596	1			T1	2		T17	3		T30	9
valid_sources[0x13]	676	1			T1	1		T16	1		T30	5
valid_sources[0x14]	524	1			T30	11		T28	13		T46	15
valid_sources[0x15]	569	1			T6	2		T30	10		T28	7
valid_sources[0x16]	677	1			T30	19		T28	10		T46	19
valid_sources[0x17]	639	1			T1	2		T30	7		T28	11
valid_sources[0x18]	759	1			T30	13		T28	7		T8	1
valid_sources[0x19]	689	1			T30	8		T28	10		T46	29
valid_sources[0x1a]	766	1			T19	1		T30	29		T28	10
valid_sources[0x1b]	664	1			T1	1		T30	4		T28	6
valid_sources[0x1c]	619	1			T1	1		T30	15		T28	10
valid_sources[0x1d]	650	1			T1	1		T19	1		T30	31
valid_sources[0x1e]	688	1			T30	1		T28	9		T46	22
valid_sources[0x1f]	887	1			T1	1		T30	8		T28	7
valid_sources[0x20]	645	1			T30	12		T28	16		T46	24
valid_sources[0x21]	814	1			T1	1		T17	1		T19	1
valid_sources[0x22]	767	1			T1	1		T32	1		T30	44
valid_sources[0x23]	620	1			T6	2		T30	1		T28	8
valid_sources[0x24]	723	1			T30	17		T28	5		T46	22
valid_sources[0x25]	770	1			T1	1		T30	9		T28	14
valid_sources[0x26]	955	1			T30	13		T28	4		T45	8
valid_sources[0x27]	641	1			T30	10		T28	14		T7	3
valid_sources[0x28]	559	1			T1	1		T30	13		T28	7
valid_sources[0x29]	594	1			T1	1		T19	2		T30	24
valid_sources[0x2a]	733	1			T4	5		T30	14		T28	21
valid_sources[0x2b]	845	1			T1	1		T30	21		T28	9
valid_sources[0x2c]	769	1			T30	16		T28	15		T46	37
valid_sources[0x2d]	585	1			T1	1		T30	7		T28	8
valid_sources[0x2e]	672	1			T30	5		T28	12		T8	3
valid_sources[0x2f]	653	1			T30	30		T28	12		T46	23
valid_sources[0x30]	545	1			T28	10		T8	1		T136	8
valid_sources[0x31]	990	1			T1	2		T2	3		T22	1
valid_sources[0x32]	657	1			T1	1		T30	49		T28	7
valid_sources[0x33]	787	1			T30	19		T28	16		T98	1
valid_sources[0x34]	486	1			T30	12		T28	4		T8	2
valid_sources[0x35]	679	1			T30	13		T28	12		T55	3
valid_sources[0x36]	770	1			T30	35		T28	10		T137	1
valid_sources[0x37]	819	1			T1	1		T22	1		T30	11
valid_sources[0x38]	757	1			T30	2		T28	5		T8	2
valid_sources[0x39]	534	1			T30	9		T28	12		T31	1
valid_sources[0x3a]	744	1			T19	1		T30	22		T28	11
valid_sources[0x3b]	711	1			T1	1		T6	3		T30	6
valid_sources[0x3c]	765	1			T30	42		T28	7		T46	29
valid_sources[0x3d]	907	1			T1	1		T30	11		T28	14
valid_sources[0x3e]	835	1			T1	1		T30	10		T28	15
valid_sources[0x3f]	886	1			T1	2		T30	11		T28	5
valid_sources[0x40]	695	1			T1	1		T30	9		T28	9
valid_sources[0x41]	609	1			T1	1		T5	2		T19	1
valid_sources[0x42]	731	1			T1	2		T30	30		T28	8
valid_sources[0x43]	1158	1			T13	1		T30	18		T28	12
valid_sources[0x44]	546	1			T1	2		T30	15		T28	6
valid_sources[0x45]	684	1			T30	9		T28	7		T29	22
valid_sources[0x46]	927	1			T30	21		T28	9		T8	1
valid_sources[0x47]	898	1			T1	1		T30	92		T28	11
valid_sources[0x48]	702	1			T1	2		T22	1		T18	2
valid_sources[0x49]	693	1			T1	1		T30	17		T28	3
valid_sources[0x4a]	626	1			T1	1		T30	12		T28	8
valid_sources[0x4b]	854	1			T22	1		T30	38		T28	12
valid_sources[0x4c]	546	1			T30	6		T28	9		T55	2
valid_sources[0x4d]	831	1			T30	3		T28	10		T46	28
valid_sources[0x4e]	659	1			T1	1		T30	16		T28	8
valid_sources[0x4f]	904	1			T19	1		T30	45		T28	7
valid_sources[0x50]	756	1			T30	10		T28	10		T46	33
valid_sources[0x51]	600	1			T1	1		T30	38		T28	15
valid_sources[0x52]	845	1			T18	1		T30	15		T28	13
valid_sources[0x53]	775	1			T1	1		T6	1		T30	16
valid_sources[0x54]	641	1			T1	2		T30	26		T28	7
valid_sources[0x55]	738	1			T1	1		T30	19		T28	5
valid_sources[0x56]	612	1			T1	2		T30	11		T28	9
valid_sources[0x57]	669	1			T30	35		T28	8		T8	1
valid_sources[0x58]	691	1			T1	1		T30	6		T28	6
valid_sources[0x59]	756	1			T30	6		T28	7		T8	1
valid_sources[0x5a]	581	1			T30	33		T28	15		T8	4
valid_sources[0x5b]	979	1			T1	1		T30	19		T28	16
valid_sources[0x5c]	865	1			T1	1		T30	41		T28	15
valid_sources[0x5d]	537	1			T30	2		T28	7		T97	1
valid_sources[0x5e]	474	1			T1	2		T6	1		T30	9
valid_sources[0x5f]	555	1			T30	6		T28	7		T55	1
valid_sources[0x60]	666	1			T30	19		T28	11		T23	2
valid_sources[0x61]	622	1			T30	18		T28	10		T8	1
valid_sources[0x62]	747	1			T30	9		T28	12		T46	32
valid_sources[0x63]	619	1			T1	2		T19	1		T30	11
valid_sources[0x64]	663	1			T6	2		T17	1		T30	24
valid_sources[0x65]	653	1			T1	1		T30	38		T28	13
valid_sources[0x66]	760	1			T30	35		T28	11		T46	16
valid_sources[0x67]	775	1			T30	19		T28	15		T46	25
valid_sources[0x68]	539	1			T1	1		T6	1		T30	8
valid_sources[0x69]	609	1			T19	1		T30	15		T28	6
valid_sources[0x6a]	673	1			T30	21		T28	12		T8	1
valid_sources[0x6b]	467	1			T30	3		T28	9		T46	29
valid_sources[0x6c]	655	1			T30	11		T28	13		T55	2
valid_sources[0x6d]	526	1			T30	36		T28	12		T46	35
valid_sources[0x6e]	830	1			T1	1		T10	2		T30	1
valid_sources[0x6f]	957	1			T1	3		T30	25		T28	9
valid_sources[0x70]	603	1			T6	8		T30	16		T28	7
valid_sources[0x71]	828	1			T1	2		T30	27		T28	4
valid_sources[0x72]	1002	1			T12	1		T30	2		T28	7
valid_sources[0x73]	608	1			T1	1		T18	2		T30	27
valid_sources[0x74]	636	1			T19	1		T30	26		T28	13
valid_sources[0x75]	579	1			T1	1		T6	2		T30	20
valid_sources[0x76]	1064	1			T30	5		T28	13		T8	2
valid_sources[0x77]	666	1			T30	20		T28	10		T8	1
valid_sources[0x78]	844	1			T1	1		T30	43		T28	10
valid_sources[0x79]	496	1			T1	2		T30	9		T28	9
valid_sources[0x7a]	1035	1			T30	19		T28	9		T46	28
valid_sources[0x7b]	700	1			T1	3		T19	1		T30	4
valid_sources[0x7c]	815	1			T14	1		T30	13		T28	8
valid_sources[0x7d]	795	1			T30	25		T28	18		T31	143
valid_sources[0x7e]	1135	1			T1	1		T30	29		T28	3
valid_sources[0x7f]	632	1			T17	1		T18	4		T30	11
valid_sources[0x80]	635	1			T1	1		T30	6		T28	12

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

40757

1

T1

26

T30

1072

T28

629

values[0x0]

all_enables

biggest_size

54516

1

T1

15

T9

5

T11

1

values[0x1]

all_enables

biggest_size

52785

1

T1

13

T9

2

T4

1