Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16131735

1

T1

11619

T2

23171

T4

9957

full_word

153607424

1

T1

638556

T2

230241

T5

3191

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	169738799	1			T1	650175		T2	253412		T5	3191
auto[TlIntgErrCmd]	125	1			T102	9		T103	6		T104	7
auto[TlIntgErrData]	112	1			T102	5		T103	6		T104	7
auto[TlIntgErrBoth]	123	1			T102	6		T103	8		T104	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

81971826

1

T1

312967

T2

126830

T5

1546

auto[1]

87767333

1

T1

337208

T2

126582

T5

1645

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7900584	1			T1	4803		T2	11497		T4	4987
auto[TlIntgErrNone]	partial	auto[1]	8230821	1			T1	6816		T2	11674		T4	4970
auto[TlIntgErrNone]	full_word	auto[0]	74071061	1			T1	308164		T2	115333		T5	1546
auto[TlIntgErrNone]	full_word	auto[1]	79536333	1			T1	330392		T2	114908		T5	1645
auto[TlIntgErrCmd]	partial	auto[0]	59	1			T102	5		T103	2		T104	3
auto[TlIntgErrCmd]	partial	auto[1]	56	1			T102	3		T103	3		T104	4
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T103	1		T117	1		T118	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T102	1		T119	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	58	1			T102	4		T103	2		T104	5
auto[TlIntgErrData]	partial	auto[1]	42	1			T103	3		T104	1		T116	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T102	1		T103	1		T119	1
auto[TlIntgErrData]	full_word	auto[1]	7	1			T104	1		T116	1		T120	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1			T102	2		T103	6		T104	1
auto[TlIntgErrBoth]	partial	auto[1]	64	1			T102	4		T103	2		T104	5
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T115	1		T121	1		T122	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T117	1		T122	1