Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	786847	1			T1	2574		T4	6608		T6	4855
auto[1]	10869055	1			T1	531		T2	105598		T5	1546
auto[2]	603830	1			T1	1992		T4	5906		T6	3189
auto[3]	10617116	1			T1	256		T2	105445		T5	1644

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14329602	1			T1	4205		T2	175896		T5	3190
auto[1]	2120906	1			T1	568		T2	16701		T4	1580
auto[2]	2145696	1			T1	488		T2	16741		T4	1380
auto[3]	4280644	1			T1	92		T2	1705		T4	175

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9703564

1

T1

5353

T2

34

T5

3190

auto[1]

13173284

1

T2

211009

T16

2

T17

5

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	401672	1			T1	2099		T4	5487		T6	4035
auto[0]	auto[0]	auto[1]	41487	1			T1	220		T4	526		T6	369
auto[0]	auto[0]	auto[2]	41438	1			T1	231		T4	549		T6	410
auto[0]	auto[0]	auto[3]	100924	1			T1	24		T4	46		T6	41
auto[0]	auto[1]	auto[0]	3240966	1			T1	314		T2	15		T5	1546
auto[0]	auto[1]	auto[1]	349785	1			T1	164		T4	531		T6	267
auto[0]	auto[1]	auto[2]	361071	1			T1	22		T2	1		T4	84
auto[0]	auto[1]	auto[3]	500860	1			T1	31		T4	56		T6	32
auto[0]	auto[2]	auto[0]	298275	1			T1	1663		T4	5001		T6	2665
auto[0]	auto[2]	auto[1]	37527	1			T1	175		T4	479		T6	257
auto[0]	auto[2]	auto[2]	28780	1			T1	130		T4	386		T6	238
auto[0]	auto[2]	auto[3]	69820	1			T1	24		T4	40		T6	29
auto[0]	auto[3]	auto[0]	3076727	1			T1	129		T2	18		T5	1644
auto[0]	auto[3]	auto[1]	340487	1			T1	9		T4	44		T6	19
auto[0]	auto[3]	auto[2]	365099	1			T1	105		T4	361		T6	215
auto[0]	auto[3]	auto[3]	448646	1			T1	13		T4	33		T6	13
auto[1]	auto[0]	auto[0]	6652	1			T45	1		T100	530		T129	627
auto[1]	auto[0]	auto[1]	29933	1			T100	2453		T128	1		T129	2913
auto[1]	auto[0]	auto[2]	29993	1			T100	2464		T130	1		T129	2914
auto[1]	auto[0]	auto[3]	134748	1			T54	1		T100	11052		T127	4
auto[1]	auto[1]	auto[0]	3650952	1			T2	88164		T17	3		T18	1
auto[1]	auto[1]	auto[1]	657967	1			T2	7809		T95	953		T96	4227
auto[1]	auto[1]	auto[2]	639842	1			T2	8768		T8	1		T95	344
auto[1]	auto[1]	auto[3]	1467612	1			T2	841		T16	2		T95	4312
auto[1]	auto[2]	auto[0]	5834	1			T100	476		T131	1		T132	1
auto[1]	auto[2]	auto[1]	26095	1			T100	2236		T129	2636		T133	1934
auto[1]	auto[2]	auto[2]	25133	1			T100	1684		T129	2458		T134	1
auto[1]	auto[2]	auto[3]	112366	1			T100	7489		T135	1		T129	11136
auto[1]	auto[3]	auto[0]	3648524	1			T2	87699		T17	2		T18	2
auto[1]	auto[3]	auto[1]	637625	1			T2	8892		T18	1		T8	1
auto[1]	auto[3]	auto[2]	654340	1			T2	7972		T95	962		T96	4284
auto[1]	auto[3]	auto[3]	1445668	1			T2	864		T54	1		T95	4156