Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1123152805	144408	0	0
ctrl_regwen_rd_A	1123152805	10718	0	0
exec_rd_A	1123152805	9659	0	0
exec_regwen_rd_A	1123152805	10296	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123152805	144408	0	0
T7	744573	0	0	0
T8	293383	0	0	0
T20	137342	0	0	0
T23	1018	0	0	0
T24	663	0	0	0
T28	113523	2367	0	0
T30	142073	3977	0	0
T31	0	1507	0	0
T46	0	4913	0	0
T47	0	3041	0	0
T48	0	1219	0	0
T49	0	3387	0	0
T50	0	2277	0	0
T51	0	671	0	0
T52	0	1763	0	0
T53	95231	0	0	0
T54	488673	0	0	0
T55	175647	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123152805	10718	0	0
T7	744573	0	0	0
T8	293383	0	0	0
T20	137342	0	0	0
T23	1018	0	0	0
T24	663	0	0	0
T28	113523	621	0	0
T30	142073	850	0	0
T46	0	724	0	0
T51	0	160	0	0
T53	95231	0	0	0
T54	488673	0	0	0
T55	175647	0	0	0
T105	0	424	0	0
T106	0	505	0	0
T107	0	520	0	0
T108	0	597	0	0
T109	0	227	0	0
T110	0	901	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123152805	9659	0	0
T7	744573	0	0	0
T8	293383	0	0	0
T20	137342	0	0	0
T23	1018	0	0	0
T24	663	0	0	0
T28	113523	591	0	0
T30	142073	794	0	0
T46	0	604	0	0
T51	0	157	0	0
T53	95231	0	0	0
T54	488673	0	0	0
T55	175647	0	0	0
T105	0	437	0	0
T106	0	404	0	0
T107	0	451	0	0
T108	0	484	0	0
T109	0	108	0	0
T110	0	736	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1123152805	10296	0	0
T7	744573	0	0	0
T8	293383	0	0	0
T20	137342	0	0	0
T23	1018	0	0	0
T24	663	0	0	0
T28	113523	465	0	0
T30	142073	781	0	0
T46	0	646	0	0
T51	0	104	0	0
T53	95231	0	0	0
T54	488673	0	0	0
T55	175647	0	0	0
T105	0	436	0	0
T106	0	531	0	0
T107	0	390	0	0
T108	0	690	0	0
T109	0	231	0	0
T110	0	1011	0	0