Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15907633

1

T1

59452

T3

24655

T4

14211

full_word

161863023

1

T1

3193

T3

245532

T4

143031

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	177770326	1			T1	62645		T3	270187		T4	157242
auto[TlIntgErrCmd]	107	1			T101	3		T102	5		T103	2
auto[TlIntgErrData]	110	1			T101	1		T102	11		T103	5
auto[TlIntgErrBoth]	113	1			T101	6		T102	4		T103	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

85968588

1

T1

31088

T3

135466

T4

78920

auto[1]

91802068

1

T1

31557

T3

134721

T4

78322

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7807021	1			T1	30817		T3	12278		T4	7067
auto[TlIntgErrNone]	partial	auto[1]	8100306	1			T1	28635		T3	12377		T4	7144
auto[TlIntgErrNone]	full_word	auto[0]	78161406	1			T1	271		T3	123188		T4	71853
auto[TlIntgErrNone]	full_word	auto[1]	83701593	1			T1	2922		T3	122344		T4	71178
auto[TlIntgErrCmd]	partial	auto[0]	51	1			T101	1		T103	1		T114	4
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T101	2		T102	4		T103	1
auto[TlIntgErrCmd]	full_word	auto[0]	2	1			T116	2		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T102	1		T114	1		T120	1
auto[TlIntgErrData]	partial	auto[0]	60	1			T101	1		T102	6		T103	4
auto[TlIntgErrData]	partial	auto[1]	42	1			T102	1		T103	1		T112	1
auto[TlIntgErrData]	full_word	auto[0]	4	1			T102	1		T113	1		T121	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T102	3		T122	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	40	1			T101	5		T102	2		T103	1
auto[TlIntgErrBoth]	partial	auto[1]	65	1			T101	1		T102	2		T103	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T123	2		T124	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T117	1		T125	2