Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	700873	1			T17	1		T15	8082		T16	24130
auto[1]	10752377	1			T1	29608		T3	112551		T4	53533
auto[2]	550316	1			T15	5591		T16	20964		T9	2041
auto[3]	10475821	1			T1	30105		T3	112064		T4	53167

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14301342	1			T1	296		T3	187168		T4	88997
auto[1]	2027036	1			T1	2882		T3	17902		T4	8483
auto[2]	2056658	1			T1	5438		T3	17853		T4	8428
auto[3]	4094351	1			T1	51097		T3	1692		T4	792

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9505389

1

T1

59712

T3

38

T4

106697

auto[1]

12973998

1

T1

1

T3

224577

T4

3

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	186179	1			T17	1		T15	1		T9	2430
auto[0]	auto[0]	auto[1]	19884	1			T15	62		T16	2		T9	262
auto[0]	auto[0]	auto[2]	19977	1			T15	68		T16	1		T9	254
auto[0]	auto[0]	auto[3]	111903	1			T15	7951		T16	7		T9	19
auto[0]	auto[1]	auto[0]	3299839	1			T1	24		T3	19		T4	44706
auto[0]	auto[1]	auto[1]	342452	1			T1	232		T3	1		T4	4039
auto[0]	auto[1]	auto[2]	372714	1			T1	2922		T3	2		T4	4388
auto[0]	auto[1]	auto[3]	551618	1			T1	26430		T3	1		T4	400
auto[0]	auto[2]	auto[0]	136585	1			T15	4		T9	1734		T137	6
auto[0]	auto[2]	auto[1]	22828	1			T15	657		T9	190		T138	2
auto[0]	auto[2]	auto[2]	14667	1			T15	36		T16	3		T9	103
auto[0]	auto[2]	auto[3]	77050	1			T15	4894		T16	6		T9	14
auto[0]	auto[3]	auto[0]	3141587	1			T1	272		T3	13		T4	44290
auto[0]	auto[3]	auto[1]	351622	1			T1	2650		T3	1		T4	4443
auto[0]	auto[3]	auto[2]	365124	1			T1	2516		T3	1		T4	4040
auto[0]	auto[3]	auto[3]	491360	1			T1	24666		T4	391		T11	60
auto[1]	auto[0]	auto[0]	11838	1			T16	801		T136	149		T139	1
auto[1]	auto[0]	auto[1]	54069	1			T16	3650		T136	693		T140	2768
auto[1]	auto[0]	auto[2]	54078	1			T16	3582		T136	661		T140	2705
auto[1]	auto[0]	auto[3]	242945	1			T16	16087		T88	6		T136	3036
auto[1]	auto[1]	auto[0]	3757824	1			T3	93916		T8	1		T141	1
auto[1]	auto[1]	auto[1]	612123	1			T3	8442		T8	1		T72	7674
auto[1]	auto[1]	auto[2]	583177	1			T3	9349		T72	8502		T39	4847
auto[1]	auto[1]	auto[3]	1232630	1			T3	821		T72	766		T39	420
auto[1]	auto[2]	auto[0]	10507	1			T16	714		T136	97		T140	514
auto[1]	auto[2]	auto[1]	47334	1			T16	3351		T136	457		T140	2499
auto[1]	auto[2]	auto[2]	43679	1			T16	3070		T136	713		T140	2196
auto[1]	auto[2]	auto[3]	197666	1			T16	13820		T136	3366		T140	10165
auto[1]	auto[3]	auto[0]	3756983	1			T3	93220		T4	1		T12	2
auto[1]	auto[3]	auto[1]	576724	1			T3	9458		T4	1		T12	1
auto[1]	auto[3]	auto[2]	603242	1			T3	8501		T44	1		T72	7679
auto[1]	auto[3]	auto[3]	1189179	1			T1	1		T3	870		T4	1