Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1096741222	126600	0	0
ctrl_regwen_rd_A	1096741222	6738	0	0
exec_rd_A	1096741222	6318	0	0
exec_regwen_rd_A	1096741222	6688	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096741222	126600	0	0
T9	404870	0	0	0
T16	165106	0	0	0
T21	39671	919	0	0
T31	0	2543	0	0
T32	0	712	0	0
T33	99874	0	0	0
T45	0	2085	0	0
T46	0	3141	0	0
T47	0	482	0	0
T48	0	2836	0	0
T49	0	4356	0	0
T50	0	2139	0	0
T51	0	1551	0	0
T52	143417	0	0	0
T53	123694	0	0	0
T54	659307	0	0	0
T55	46631	0	0	0
T56	688921	0	0	0
T57	71111	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096741222	6738	0	0
T9	404870	0	0	0
T16	165106	0	0	0
T21	39671	177	0	0
T33	99874	0	0	0
T47	0	130	0	0
T52	143417	0	0	0
T53	123694	0	0	0
T54	659307	0	0	0
T55	46631	0	0	0
T56	688921	0	0	0
T57	71111	0	0	0
T104	0	295	0	0
T105	0	976	0	0
T106	0	460	0	0
T107	0	254	0	0
T108	0	54	0	0
T109	0	841	0	0
T110	0	161	0	0
T111	0	334	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096741222	6318	0	0
T9	404870	0	0	0
T16	165106	0	0	0
T21	39671	135	0	0
T33	99874	0	0	0
T47	0	108	0	0
T52	143417	0	0	0
T53	123694	0	0	0
T54	659307	0	0	0
T55	46631	0	0	0
T56	688921	0	0	0
T57	71111	0	0	0
T104	0	209	0	0
T105	0	922	0	0
T106	0	485	0	0
T107	0	251	0	0
T108	0	80	0	0
T109	0	573	0	0
T110	0	174	0	0
T111	0	359	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1096741222	6688	0	0
T9	404870	0	0	0
T16	165106	0	0	0
T21	39671	245	0	0
T33	99874	0	0	0
T47	0	152	0	0
T52	143417	0	0	0
T53	123694	0	0	0
T54	659307	0	0	0
T55	46631	0	0	0
T56	688921	0	0	0
T57	71111	0	0	0
T104	0	242	0	0
T105	0	939	0	0
T106	0	530	0	0
T107	0	231	0	0
T108	0	162	0	0
T109	0	789	0	0
T110	0	148	0	0
T111	0	304	0	0