Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16275894	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

168142065

1

T1

10000

T2

42343

T3

5657

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90894100	1			T1	4987		T2	116805		T3	2843
values[0x0]	45139055	1			T1	2504		T2	39401		T3	1425
values[0x1]	48384804	1			T1	2509		T2	77539		T3	1389

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8275391	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

176142568

1

T1

10000

T2

138422

T3

5657

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	572058	1			T2	944		T4	225		T12	24
valid_sources[0x01]	561102	1			T2	1205		T4	234		T12	18
valid_sources[0x02]	601129	1			T2	926		T4	254		T12	24
valid_sources[0x03]	638580	1			T2	1071		T4	226		T12	21
valid_sources[0x04]	604481	1			T2	927		T4	236		T12	28
valid_sources[0x05]	620800	1			T2	871		T4	231		T12	30
valid_sources[0x06]	625718	1			T2	1025		T4	262		T12	25
valid_sources[0x07]	589172	1			T2	880		T4	247		T12	18
valid_sources[0x08]	550979	1			T2	1007		T4	259		T12	20
valid_sources[0x09]	579033	1			T2	1021		T4	216		T12	29
valid_sources[0x0a]	614802	1			T2	975		T4	269		T12	22
valid_sources[0x0b]	575443	1			T2	1125		T4	260		T12	26
valid_sources[0x0c]	560219	1			T2	896		T4	307		T12	30
valid_sources[0x0d]	2633921	1			T2	972		T4	268		T12	35
valid_sources[0x0e]	551270	1			T2	914		T4	278		T12	20
valid_sources[0x0f]	553379	1			T2	964		T4	305		T12	28
valid_sources[0x10]	572670	1			T2	826		T4	252		T12	32
valid_sources[0x11]	612868	1			T2	1045		T4	243		T12	16
valid_sources[0x12]	1626272	1			T2	996		T4	265		T12	26
valid_sources[0x13]	561627	1			T2	1278		T4	242		T12	21
valid_sources[0x14]	698718	1			T2	859		T4	222		T12	21
valid_sources[0x15]	560663	1			T2	832		T4	266		T12	32
valid_sources[0x16]	560257	1			T2	742		T4	265		T12	26
valid_sources[0x17]	605858	1			T2	911		T4	234		T12	37
valid_sources[0x18]	569323	1			T1	5000		T2	875		T4	269
valid_sources[0x19]	603265	1			T2	859		T4	246		T12	17
valid_sources[0x1a]	2823140	1			T2	800		T4	220		T12	35
valid_sources[0x1b]	575244	1			T2	850		T4	269		T12	26
valid_sources[0x1c]	1172735	1			T2	775		T4	275		T12	32
valid_sources[0x1d]	617507	1			T2	1098		T4	246		T12	27
valid_sources[0x1e]	571398	1			T2	1009		T4	237		T12	29
valid_sources[0x1f]	586785	1			T2	654		T4	249		T12	20
valid_sources[0x20]	583555	1			T2	906		T4	246		T12	23
valid_sources[0x21]	704555	1			T2	953		T4	276		T12	32
valid_sources[0x22]	572873	1			T2	897		T4	251		T12	11
valid_sources[0x23]	571303	1			T2	703		T4	210		T12	17
valid_sources[0x24]	610968	1			T2	1086		T4	197		T12	26
valid_sources[0x25]	562150	1			T2	1026		T3	2828		T4	224
valid_sources[0x26]	554649	1			T2	748		T4	272		T12	20
valid_sources[0x27]	572230	1			T2	800		T4	233		T12	34
valid_sources[0x28]	707666	1			T2	1130		T4	273		T12	27
valid_sources[0x29]	594119	1			T2	920		T4	242		T12	22
valid_sources[0x2a]	634884	1			T2	1004		T4	235		T12	34
valid_sources[0x2b]	552219	1			T2	1024		T4	263		T12	22
valid_sources[0x2c]	577977	1			T2	745		T4	240		T12	30
valid_sources[0x2d]	582124	1			T1	5000		T2	1016		T4	238
valid_sources[0x2e]	557911	1			T2	845		T4	228		T12	39
valid_sources[0x2f]	649391	1			T2	1037		T4	261		T12	28
valid_sources[0x30]	2020955	1			T2	932		T4	273		T12	22
valid_sources[0x31]	558581	1			T2	865		T4	227		T12	18
valid_sources[0x32]	603233	1			T2	757		T4	217		T12	19
valid_sources[0x33]	584772	1			T2	1100		T4	206		T12	25
valid_sources[0x34]	611542	1			T2	878		T4	221		T12	21
valid_sources[0x35]	571092	1			T2	964		T4	252		T12	16
valid_sources[0x36]	608310	1			T2	884		T4	257		T12	24
valid_sources[0x37]	594291	1			T2	934		T4	310		T12	23
valid_sources[0x38]	566048	1			T2	641		T4	284		T12	28
valid_sources[0x39]	600397	1			T2	776		T4	241		T12	21
valid_sources[0x3a]	552679	1			T2	1028		T4	270		T12	26
valid_sources[0x3b]	632187	1			T2	819		T4	240		T12	21
valid_sources[0x3c]	578328	1			T2	942		T4	233		T12	32
valid_sources[0x3d]	584871	1			T2	918		T4	239		T12	38
valid_sources[0x3e]	587917	1			T2	943		T4	257		T12	25
valid_sources[0x3f]	601361	1			T2	945		T4	231		T12	23
valid_sources[0x40]	565570	1			T2	981		T4	296		T12	30
valid_sources[0x41]	593548	1			T2	974		T4	252		T12	36
valid_sources[0x42]	552485	1			T2	1055		T4	235		T12	29
valid_sources[0x43]	595430	1			T2	1151		T4	254		T12	26
valid_sources[0x44]	1754209	1			T2	1196		T4	217		T12	29
valid_sources[0x45]	561963	1			T2	877		T4	275		T12	29
valid_sources[0x46]	2020053	1			T2	1031		T4	273		T12	23
valid_sources[0x47]	672595	1			T2	986		T4	255		T12	36
valid_sources[0x48]	617760	1			T2	766		T4	244		T12	28
valid_sources[0x49]	606622	1			T2	963		T4	258		T12	26
valid_sources[0x4a]	573858	1			T2	1095		T4	240		T12	25
valid_sources[0x4b]	713038	1			T2	920		T4	268		T12	31
valid_sources[0x4c]	623371	1			T2	970		T4	260		T12	32
valid_sources[0x4d]	561482	1			T2	906		T4	242		T12	30
valid_sources[0x4e]	605616	1			T2	813		T4	263		T12	18
valid_sources[0x4f]	674813	1			T2	900		T4	244		T12	20
valid_sources[0x50]	676531	1			T2	751		T4	283		T12	33
valid_sources[0x51]	560680	1			T2	773		T4	225		T12	31
valid_sources[0x52]	643666	1			T2	1145		T4	233		T12	27
valid_sources[0x53]	616113	1			T2	823		T4	258		T12	27
valid_sources[0x54]	568899	1			T2	1071		T4	278		T12	21
valid_sources[0x55]	562299	1			T2	849		T4	249		T12	30
valid_sources[0x56]	581672	1			T2	696		T4	279		T12	20
valid_sources[0x57]	576367	1			T2	1149		T4	260		T12	27
valid_sources[0x58]	599590	1			T2	993		T4	238		T12	26
valid_sources[0x59]	588848	1			T2	866		T4	256		T12	23
valid_sources[0x5a]	563552	1			T2	1031		T4	240		T12	35
valid_sources[0x5b]	610004	1			T2	888		T4	255		T12	33
valid_sources[0x5c]	574554	1			T2	970		T4	217		T12	27
valid_sources[0x5d]	823291	1			T2	791		T4	210		T12	37
valid_sources[0x5e]	563904	1			T2	891		T4	228		T12	24
valid_sources[0x5f]	602051	1			T2	984		T4	233		T12	23
valid_sources[0x60]	564240	1			T2	994		T4	253		T12	26
valid_sources[0x61]	593668	1			T2	837		T4	242		T12	38
valid_sources[0x62]	601448	1			T2	1060		T4	270		T12	34
valid_sources[0x63]	549665	1			T2	962		T4	234		T12	19
valid_sources[0x64]	563180	1			T2	776		T4	254		T12	27
valid_sources[0x65]	613487	1			T2	1068		T4	252		T12	31
valid_sources[0x66]	556270	1			T2	768		T4	248		T12	24
valid_sources[0x67]	664854	1			T2	1138		T4	260		T12	25
valid_sources[0x68]	589724	1			T2	798		T4	216		T12	26
valid_sources[0x69]	560092	1			T2	1001		T4	220		T12	25
valid_sources[0x6a]	624580	1			T2	1015		T4	250		T12	10
valid_sources[0x6b]	665884	1			T2	894		T4	274		T12	33
valid_sources[0x6c]	664125	1			T2	981		T4	258		T12	21
valid_sources[0x6d]	564911	1			T2	961		T4	260		T12	15
valid_sources[0x6e]	611644	1			T2	956		T4	274		T12	30
valid_sources[0x6f]	579512	1			T2	906		T4	300		T12	41
valid_sources[0x70]	607866	1			T2	1030		T4	208		T12	26
valid_sources[0x71]	626704	1			T2	915		T4	256		T12	15
valid_sources[0x72]	636859	1			T2	607		T4	251		T12	20
valid_sources[0x73]	1700728	1			T2	925		T4	253		T12	32
valid_sources[0x74]	702823	1			T2	942		T4	291		T12	18
valid_sources[0x75]	681360	1			T2	884		T4	239		T12	31
valid_sources[0x76]	576881	1			T2	917		T4	252		T12	28
valid_sources[0x77]	561674	1			T2	1047		T4	242		T12	35
valid_sources[0x78]	581137	1			T2	901		T4	254		T12	26
valid_sources[0x79]	624334	1			T2	721		T4	234		T12	26
valid_sources[0x7a]	558908	1			T2	923		T4	229		T12	21
valid_sources[0x7b]	548552	1			T2	926		T4	246		T12	34
valid_sources[0x7c]	603501	1			T2	1098		T4	293		T12	18
valid_sources[0x7d]	595951	1			T2	968		T4	281		T12	27
valid_sources[0x7e]	631889	1			T2	1008		T4	245		T12	26
valid_sources[0x7f]	571642	1			T2	774		T4	235		T12	32
valid_sources[0x80]	591193	1			T2	884		T4	247		T12	34

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

82715814

1

T1

4987

T2

21054

T3

2843

values[0x0]

all_enables

biggest_size

42709607

1

T1

2504

T2

10667

T3

1425

values[0x1]

all_enables

biggest_size

42716644

1

T1

2509

T2

10622

T3

1389

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34762	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

159050

1

T1

1

T2

2

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	55560	1			T19	634		T11	80		T20	7
values[0x0]	66784	1			T2	2		T3	2		T4	5
values[0x1]	71468	1			T1	2		T2	2		T4	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26214	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

167598

1

T1

1

T2

3

T3

1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	630	1			T34	18		T35	6		T49	6
valid_sources[0x01]	506	1			T4	1		T20	1		T8	1
valid_sources[0x02]	580	1			T8	2		T23	1		T34	20
valid_sources[0x03]	1198	1			T6	1		T89	1		T34	13
valid_sources[0x04]	667	1			T38	1		T34	20		T35	16
valid_sources[0x05]	573	1			T19	1		T121	1		T34	25
valid_sources[0x06]	739	1			T34	22		T58	1		T35	15
valid_sources[0x07]	558	1			T11	1		T34	22		T35	16
valid_sources[0x08]	564	1			T11	1		T34	29		T58	3
valid_sources[0x09]	722	1			T44	1		T34	30		T35	11
valid_sources[0x0a]	707	1			T40	1		T34	31		T58	1
valid_sources[0x0b]	550	1			T4	1		T19	3		T34	18
valid_sources[0x0c]	804	1			T90	7		T34	21		T35	12
valid_sources[0x0d]	812	1			T18	13		T11	2		T8	1
valid_sources[0x0e]	908	1			T122	12		T34	38		T58	1
valid_sources[0x0f]	676	1			T34	27		T35	17		T49	14
valid_sources[0x10]	599	1			T19	7		T34	16		T35	11
valid_sources[0x11]	667	1			T34	30		T35	5		T49	4
valid_sources[0x12]	661	1			T23	1		T34	19		T35	9
valid_sources[0x13]	655	1			T8	1		T23	2		T34	23
valid_sources[0x14]	701	1			T8	1		T34	21		T35	5
valid_sources[0x15]	675	1			T5	1		T19	6		T20	3
valid_sources[0x16]	1423	1			T22	1		T8	1		T34	26
valid_sources[0x17]	586	1			T19	3		T9	24		T34	28
valid_sources[0x18]	856	1			T34	40		T35	10		T49	20
valid_sources[0x19]	802	1			T19	1		T46	1		T120	1
valid_sources[0x1a]	614	1			T19	1		T9	4		T23	1
valid_sources[0x1b]	691	1			T4	2		T11	1		T34	25
valid_sources[0x1c]	696	1			T34	17		T58	2		T35	10
valid_sources[0x1d]	616	1			T34	39		T35	9		T49	13
valid_sources[0x1e]	626	1			T13	1		T34	31		T35	15
valid_sources[0x1f]	821	1			T19	1		T34	23		T35	17
valid_sources[0x20]	898	1			T34	30		T35	19		T49	17
valid_sources[0x21]	662	1			T34	29		T35	16		T51	2
valid_sources[0x22]	588	1			T22	1		T34	29		T35	10
valid_sources[0x23]	664	1			T19	1		T34	33		T35	16
valid_sources[0x24]	786	1			T19	132		T8	1		T36	2
valid_sources[0x25]	848	1			T16	2		T19	110		T11	1
valid_sources[0x26]	640	1			T34	22		T58	2		T35	10
valid_sources[0x27]	650	1			T9	1		T34	25		T35	9
valid_sources[0x28]	663	1			T11	3		T34	30		T35	13
valid_sources[0x29]	798	1			T19	1		T8	1		T9	1
valid_sources[0x2a]	784	1			T31	1		T34	32		T58	2
valid_sources[0x2b]	786	1			T5	1		T19	7		T11	1
valid_sources[0x2c]	885	1			T47	2		T34	12		T35	9
valid_sources[0x2d]	690	1			T11	1		T120	1		T34	48
valid_sources[0x2e]	675	1			T21	1		T34	17		T58	2
valid_sources[0x2f]	567	1			T34	18		T35	9		T49	16
valid_sources[0x30]	945	1			T34	45		T58	2		T35	3
valid_sources[0x31]	752	1			T19	145		T34	36		T35	18
valid_sources[0x32]	631	1			T34	10		T35	11		T49	5
valid_sources[0x33]	617	1			T19	1		T11	4		T37	1
valid_sources[0x34]	1045	1			T29	1		T19	18		T8	1
valid_sources[0x35]	711	1			T21	1		T23	1		T34	30
valid_sources[0x36]	663	1			T28	1		T48	1		T34	19
valid_sources[0x37]	677	1			T31	4		T34	22		T58	3
valid_sources[0x38]	637	1			T34	33		T58	1		T35	6
valid_sources[0x39]	801	1			T89	1		T34	26		T35	10
valid_sources[0x3a]	682	1			T34	20		T58	1		T35	14
valid_sources[0x3b]	786	1			T6	1		T19	84		T11	1
valid_sources[0x3c]	923	1			T8	1		T123	1		T34	34
valid_sources[0x3d]	895	1			T19	197		T34	28		T35	19
valid_sources[0x3e]	593	1			T5	1		T34	18		T35	11
valid_sources[0x3f]	739	1			T8	2		T23	1		T34	37
valid_sources[0x40]	803	1			T21	1		T11	2		T34	19
valid_sources[0x41]	645	1			T11	2		T34	16		T58	1
valid_sources[0x42]	863	1			T89	1		T11	2		T34	24
valid_sources[0x43]	755	1			T28	4		T9	3		T34	15
valid_sources[0x44]	662	1			T8	2		T34	15		T35	9
valid_sources[0x45]	667	1			T28	1		T19	1		T34	27
valid_sources[0x46]	600	1			T19	6		T34	24		T35	8
valid_sources[0x47]	770	1			T22	1		T121	1		T34	31
valid_sources[0x48]	668	1			T8	1		T34	31		T58	1
valid_sources[0x49]	717	1			T34	18		T35	9		T49	5
valid_sources[0x4a]	808	1			T34	23		T35	11		T49	10
valid_sources[0x4b]	834	1			T121	1		T34	23		T58	3
valid_sources[0x4c]	649	1			T11	2		T34	50		T35	18
valid_sources[0x4d]	733	1			T28	2		T9	3		T34	21
valid_sources[0x4e]	749	1			T34	24		T35	14		T49	19
valid_sources[0x4f]	735	1			T37	2		T34	24		T35	11
valid_sources[0x50]	657	1			T19	1		T9	6		T37	4
valid_sources[0x51]	811	1			T22	1		T19	1		T34	46
valid_sources[0x52]	673	1			T34	43		T35	13		T49	12
valid_sources[0x53]	727	1			T37	9		T34	28		T35	13
valid_sources[0x54]	993	1			T20	1		T8	1		T31	1
valid_sources[0x55]	699	1			T8	1		T34	25		T58	1
valid_sources[0x56]	750	1			T23	1		T34	26		T58	1
valid_sources[0x57]	790	1			T4	3		T5	1		T8	1
valid_sources[0x58]	736	1			T8	1		T34	21		T35	19
valid_sources[0x59]	514	1			T4	1		T5	1		T37	1
valid_sources[0x5a]	711	1			T28	1		T19	1		T8	1
valid_sources[0x5b]	844	1			T120	2		T34	24		T35	14
valid_sources[0x5c]	663	1			T20	1		T8	1		T124	1
valid_sources[0x5d]	696	1			T57	2		T9	20		T34	20
valid_sources[0x5e]	652	1			T19	1		T8	1		T34	24
valid_sources[0x5f]	952	1			T34	47		T35	9		T49	5
valid_sources[0x60]	841	1			T4	1		T34	39		T35	9
valid_sources[0x61]	758	1			T21	1		T11	1		T34	17
valid_sources[0x62]	937	1			T34	22		T35	18		T49	21
valid_sources[0x63]	750	1			T9	8		T34	44		T58	1
valid_sources[0x64]	964	1			T34	26		T58	2		T35	8
valid_sources[0x65]	905	1			T28	1		T11	3		T20	5
valid_sources[0x66]	1070	1			T48	1		T34	21		T35	12
valid_sources[0x67]	683	1			T91	1		T34	10		T35	9
valid_sources[0x68]	529	1			T19	1		T34	26		T58	1
valid_sources[0x69]	675	1			T8	4		T34	27		T35	12
valid_sources[0x6a]	1002	1			T19	1		T34	21		T58	1
valid_sources[0x6b]	783	1			T11	1		T34	33		T58	2
valid_sources[0x6c]	634	1			T19	65		T34	10		T35	25
valid_sources[0x6d]	763	1			T19	27		T11	1		T34	28
valid_sources[0x6e]	634	1			T5	1		T19	3		T34	22
valid_sources[0x6f]	778	1			T29	1		T34	21		T35	15
valid_sources[0x70]	993	1			T28	1		T19	104		T23	1
valid_sources[0x71]	824	1			T48	1		T34	24		T35	12
valid_sources[0x72]	951	1			T15	4		T121	1		T34	36
valid_sources[0x73]	711	1			T19	1		T34	24		T35	13
valid_sources[0x74]	784	1			T19	130		T8	1		T34	38
valid_sources[0x75]	728	1			T21	1		T8	1		T34	28
valid_sources[0x76]	828	1			T19	92		T11	4		T36	6
valid_sources[0x77]	777	1			T19	127		T11	1		T34	13
valid_sources[0x78]	650	1			T34	41		T35	17		T49	11
valid_sources[0x79]	670	1			T19	11		T125	1		T34	19
valid_sources[0x7a]	954	1			T89	1		T34	24		T35	5
valid_sources[0x7b]	788	1			T11	2		T8	1		T48	1
valid_sources[0x7c]	781	1			T34	33		T35	8		T49	20
valid_sources[0x7d]	550	1			T34	12		T35	10		T49	8
valid_sources[0x7e]	722	1			T34	18		T35	6		T49	5
valid_sources[0x7f]	795	1			T34	38		T58	1		T35	10
valid_sources[0x80]	657	1			T19	1		T120	1		T34	28

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43280

1

T19

598

T20

4

T8

19

values[0x0]

all_enables

biggest_size

58678

1

T2

2

T3

1

T4

3

values[0x1]

all_enables

biggest_size

57092

1

T1

1

T12

1

T5

2