Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16183851

1

T2

191402

T4

5765

T5

7583

full_word

164876428

1

T1

10000

T2

42343

T3

5657

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	181060019	1			T1	10000		T2	233745		T3	5657
auto[TlIntgErrCmd]	76	1			T95	2		T96	2		T97	2
auto[TlIntgErrData]	89	1			T95	2		T96	3		T97	3
auto[TlIntgErrBoth]	95	1			T95	6		T96	5		T97	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87426632

1

T1

4987

T2

116805

T3

2843

auto[1]

93633647

1

T1

5013

T2

116940

T3

2814

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7906485	1			T2	95751		T4	2897		T5	3864
auto[TlIntgErrNone]	partial	auto[1]	8277136	1			T2	95651		T4	2868		T5	3719
auto[TlIntgErrNone]	full_word	auto[0]	79520039	1			T1	4987		T2	21054		T3	2843
auto[TlIntgErrNone]	full_word	auto[1]	85356359	1			T1	5013		T2	21289		T3	2814
auto[TlIntgErrCmd]	partial	auto[0]	22	1			T96	1		T109	2		T112	2
auto[TlIntgErrCmd]	partial	auto[1]	41	1			T95	1		T96	1		T97	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T95	1		T113	1		T111	1
auto[TlIntgErrCmd]	full_word	auto[1]	10	1			T97	1		T109	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	43	1			T95	2		T96	2		T97	1
auto[TlIntgErrData]	partial	auto[1]	38	1			T96	1		T97	1		T106	2
auto[TlIntgErrData]	full_word	auto[0]	1	1			T114	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	7	1			T97	1		T110	1		T113	1
auto[TlIntgErrBoth]	partial	auto[0]	36	1			T95	3		T96	1		T106	2
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T95	3		T96	4		T97	4
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T107	1		T115	1		T116	1
auto[TlIntgErrBoth]	full_word	auto[1]	6	1			T97	1		T106	1		T108	1