Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1042401	1			T6	35424		T7	4235		T15	16576
auto[1]	10848957	1			T1	4984		T2	98076		T3	2843
auto[2]	812456	1			T6	25524		T7	3940		T15	16603
auto[3]	10528143	1			T1	5012		T2	98239		T3	2813

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14816806	1			T1	9996		T2	6452		T3	5656
auto[1]	2108911	1			T2	29081		T4	3272		T5	2276
auto[2]	2135775	1			T2	29262		T4	3354		T5	2239
auto[3]	4170465	1			T2	131520		T4	304		T5	225

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10248130

1

T1

9995

T3

5656

T4

40390

auto[1]

12983827

1

T1

1

T2

196315

T4

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	407106	1			T15	1		T8	21		T120	3975
auto[0]	auto[0]	auto[1]	42437	1			T7	38		T8	1		T120	411
auto[0]	auto[0]	auto[2]	42481	1			T7	35		T15	1		T8	2
auto[0]	auto[0]	auto[3]	96816	1			T7	4161		T120	43		T70	887
auto[0]	auto[1]	auto[0]	3415393	1			T1	4983		T3	2843		T4	16574
auto[0]	auto[1]	auto[1]	367655	1			T4	1641		T5	1178		T13	32
auto[0]	auto[1]	auto[2]	386745	1			T4	1724		T5	1141		T13	44
auto[0]	auto[1]	auto[3]	556036	1			T4	140		T5	119		T13	6
auto[0]	auto[2]	auto[0]	307668	1			T7	4		T8	20		T9	1
auto[0]	auto[2]	auto[1]	38330	1			T7	234		T15	1		T8	3
auto[0]	auto[2]	auto[2]	30379	1			T7	27		T120	443		T70	120
auto[0]	auto[2]	auto[3]	69938	1			T7	3675		T120	50		T70	579
auto[0]	auto[3]	auto[0]	3236739	1			T1	5012		T3	2813		T4	16886
auto[0]	auto[3]	auto[1]	361609	1			T4	1631		T5	1098		T13	42
auto[0]	auto[3]	auto[2]	385128	1			T4	1630		T5	1098		T13	42
auto[0]	auto[3]	auto[3]	503670	1			T4	164		T5	106		T13	6
auto[1]	auto[0]	auto[0]	15019	1			T6	1182		T15	564		T92	652
auto[1]	auto[0]	auto[1]	67514	1			T6	5315		T15	2463		T92	3169
auto[1]	auto[0]	auto[2]	67823	1			T6	5295		T15	2523		T92	3120
auto[1]	auto[0]	auto[3]	303205	1			T6	23632		T7	1		T15	11024
auto[1]	auto[1]	auto[0]	3712743	1			T1	1		T2	3252		T6	199
auto[1]	auto[1]	auto[1]	613820	1			T2	14418		T6	5244		T89	7004
auto[1]	auto[1]	auto[2]	567588	1			T2	14627		T6	858		T89	6946
auto[1]	auto[1]	auto[3]	1228977	1			T2	65779		T6	23821		T89	686
auto[1]	auto[2]	auto[0]	12782	1			T6	1071		T15	349		T92	640
auto[1]	auto[2]	auto[1]	58223	1			T6	4950		T15	1453		T92	2885
auto[1]	auto[2]	auto[2]	53615	1			T6	3588		T15	2715		T92	2597
auto[1]	auto[2]	auto[3]	241521	1			T6	15915		T15	12085		T92	11855
auto[1]	auto[3]	auto[0]	3709356	1			T2	3200		T4	1		T6	101
auto[1]	auto[3]	auto[1]	559323	1			T2	14663		T6	509		T89	6970
auto[1]	auto[3]	auto[2]	602016	1			T2	14635		T6	3640		T14	1
auto[1]	auto[3]	auto[3]	1170302	1			T2	65741		T6	16146		T89	716