Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1232175861	159644	0	0
ctrl_regwen_rd_A	1232175861	7281	0	0
exec_rd_A	1232175861	6848	0	0
exec_regwen_rd_A	1232175861	7529	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232175861	159644	0	0
T11	22181	0	0	0
T19	84254	1830	0	0
T20	109720	0	0	0
T30	114999	0	0	0
T34	0	5709	0	0
T35	0	3438	0	0
T38	34326	0	0	0
T43	147611	0	0	0
T44	74660	0	0	0
T45	103098	0	0	0
T46	50514	0	0	0
T49	0	3744	0	0
T51	0	2651	0	0
T52	0	1055	0	0
T53	0	882	0	0
T54	0	872	0	0
T55	0	1162	0	0
T56	0	3803	0	0
T57	72993	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232175861	7281	0	0
T11	22181	0	0	0
T19	84254	398	0	0
T20	109720	0	0	0
T30	114999	0	0	0
T38	34326	0	0	0
T43	147611	0	0	0
T44	74660	0	0	0
T45	103098	0	0	0
T46	50514	0	0	0
T51	0	375	0	0
T54	0	68	0	0
T57	72993	0	0	0
T98	0	46	0	0
T99	0	191	0	0
T100	0	757	0	0
T101	0	678	0	0
T102	0	417	0	0
T103	0	360	0	0
T104	0	80	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232175861	6848	0	0
T11	22181	0	0	0
T19	84254	451	0	0
T20	109720	0	0	0
T30	114999	0	0	0
T38	34326	0	0	0
T43	147611	0	0	0
T44	74660	0	0	0
T45	103098	0	0	0
T46	50514	0	0	0
T51	0	360	0	0
T54	0	50	0	0
T57	72993	0	0	0
T98	0	90	0	0
T99	0	222	0	0
T100	0	659	0	0
T101	0	622	0	0
T102	0	347	0	0
T103	0	410	0	0
T104	0	75	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1232175861	7529	0	0
T11	22181	0	0	0
T19	84254	352	0	0
T20	109720	0	0	0
T30	114999	0	0	0
T38	34326	0	0	0
T43	147611	0	0	0
T44	74660	0	0	0
T45	103098	0	0	0
T46	50514	0	0	0
T51	0	458	0	0
T54	0	64	0	0
T57	72993	0	0	0
T98	0	98	0	0
T99	0	291	0	0
T100	0	598	0	0
T101	0	684	0	0
T102	0	347	0	0
T103	0	424	0	0
T104	0	113	0	0