| T788 |
/workspace/coverage/default/9.sram_ctrl_stress_all_with_rand_reset.833609106 |
|
|
Apr 02 02:28:54 PM PDT 24 |
Apr 02 02:30:26 PM PDT 24 |
3910109973 ps |
| T789 |
/workspace/coverage/default/42.sram_ctrl_lc_escalation.1588799116 |
|
|
Apr 02 02:40:09 PM PDT 24 |
Apr 02 02:41:48 PM PDT 24 |
38890529613 ps |
| T790 |
/workspace/coverage/default/44.sram_ctrl_partial_access.1817487901 |
|
|
Apr 02 02:40:28 PM PDT 24 |
Apr 02 02:41:07 PM PDT 24 |
2250052807 ps |
| T791 |
/workspace/coverage/default/19.sram_ctrl_max_throughput.4024470445 |
|
|
Apr 02 02:31:53 PM PDT 24 |
Apr 02 02:33:35 PM PDT 24 |
3194205399 ps |
| T792 |
/workspace/coverage/default/4.sram_ctrl_stress_pipeline.4112764214 |
|
|
Apr 02 02:27:34 PM PDT 24 |
Apr 02 02:31:16 PM PDT 24 |
8144299962 ps |
| T793 |
/workspace/coverage/default/21.sram_ctrl_bijection.1007365298 |
|
|
Apr 02 02:32:36 PM PDT 24 |
Apr 02 03:07:43 PM PDT 24 |
398033884504 ps |
| T794 |
/workspace/coverage/default/22.sram_ctrl_ram_cfg.358297977 |
|
|
Apr 02 02:33:08 PM PDT 24 |
Apr 02 02:33:12 PM PDT 24 |
375067442 ps |
| T795 |
/workspace/coverage/default/13.sram_ctrl_alert_test.224194379 |
|
|
Apr 02 02:30:00 PM PDT 24 |
Apr 02 02:30:01 PM PDT 24 |
25399080 ps |
| T796 |
/workspace/coverage/default/28.sram_ctrl_stress_all.485897791 |
|
|
Apr 02 02:35:44 PM PDT 24 |
Apr 02 03:25:42 PM PDT 24 |
51412143053 ps |
| T797 |
/workspace/coverage/default/44.sram_ctrl_bijection.3441278378 |
|
|
Apr 02 02:40:27 PM PDT 24 |
Apr 02 02:57:07 PM PDT 24 |
173612298076 ps |
| T798 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.2375264346 |
|
|
Apr 02 02:30:05 PM PDT 24 |
Apr 02 02:31:00 PM PDT 24 |
2772700519 ps |
| T799 |
/workspace/coverage/default/42.sram_ctrl_max_throughput.4232094774 |
|
|
Apr 02 02:40:10 PM PDT 24 |
Apr 02 02:41:20 PM PDT 24 |
1205563673 ps |
| T800 |
/workspace/coverage/default/1.sram_ctrl_regwen.3617626406 |
|
|
Apr 02 02:27:00 PM PDT 24 |
Apr 02 02:37:47 PM PDT 24 |
31320447903 ps |
| T801 |
/workspace/coverage/default/31.sram_ctrl_ram_cfg.3625135859 |
|
|
Apr 02 02:36:38 PM PDT 24 |
Apr 02 02:36:42 PM PDT 24 |
1402925197 ps |
| T802 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.851434848 |
|
|
Apr 02 02:28:38 PM PDT 24 |
Apr 02 02:31:12 PM PDT 24 |
2255749433 ps |
| T803 |
/workspace/coverage/default/21.sram_ctrl_stress_pipeline.2250746693 |
|
|
Apr 02 02:32:36 PM PDT 24 |
Apr 02 02:35:09 PM PDT 24 |
3153583035 ps |
| T804 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.786666800 |
|
|
Apr 02 02:39:45 PM PDT 24 |
Apr 02 02:44:16 PM PDT 24 |
50262481596 ps |
| T805 |
/workspace/coverage/default/39.sram_ctrl_ram_cfg.4125680053 |
|
|
Apr 02 02:39:44 PM PDT 24 |
Apr 02 02:39:48 PM PDT 24 |
1980218639 ps |
| T806 |
/workspace/coverage/default/24.sram_ctrl_stress_pipeline.1324590959 |
|
|
Apr 02 02:33:41 PM PDT 24 |
Apr 02 02:38:07 PM PDT 24 |
4146701679 ps |
| T807 |
/workspace/coverage/default/33.sram_ctrl_stress_all_with_rand_reset.1505708855 |
|
|
Apr 02 02:37:36 PM PDT 24 |
Apr 02 02:38:17 PM PDT 24 |
2281785396 ps |
| T808 |
/workspace/coverage/default/32.sram_ctrl_alert_test.2987253869 |
|
|
Apr 02 02:37:17 PM PDT 24 |
Apr 02 02:37:18 PM PDT 24 |
15195725 ps |
| T809 |
/workspace/coverage/default/28.sram_ctrl_access_during_key_req.3810292530 |
|
|
Apr 02 02:35:32 PM PDT 24 |
Apr 02 02:55:12 PM PDT 24 |
11223676562 ps |
| T810 |
/workspace/coverage/default/16.sram_ctrl_mem_partial_access.3241793222 |
|
|
Apr 02 02:30:52 PM PDT 24 |
Apr 02 02:33:09 PM PDT 24 |
18092811430 ps |
| T811 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.1564482392 |
|
|
Apr 02 02:33:53 PM PDT 24 |
Apr 02 02:33:56 PM PDT 24 |
365518086 ps |
| T812 |
/workspace/coverage/default/24.sram_ctrl_stress_all.1272237439 |
|
|
Apr 02 02:33:56 PM PDT 24 |
Apr 02 03:38:43 PM PDT 24 |
194635318643 ps |
| T813 |
/workspace/coverage/default/2.sram_ctrl_stress_pipeline.3051886875 |
|
|
Apr 02 02:27:10 PM PDT 24 |
Apr 02 02:31:19 PM PDT 24 |
7298228853 ps |
| T814 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2967302015 |
|
|
Apr 02 02:35:33 PM PDT 24 |
Apr 02 02:36:44 PM PDT 24 |
1601480560 ps |
| T815 |
/workspace/coverage/default/23.sram_ctrl_mem_walk.502120167 |
|
|
Apr 02 02:33:26 PM PDT 24 |
Apr 02 02:37:20 PM PDT 24 |
4109782986 ps |
| T816 |
/workspace/coverage/default/35.sram_ctrl_partial_access.702632232 |
|
|
Apr 02 02:38:06 PM PDT 24 |
Apr 02 02:38:28 PM PDT 24 |
2867637829 ps |
| T817 |
/workspace/coverage/default/10.sram_ctrl_bijection.1119030273 |
|
|
Apr 02 02:28:57 PM PDT 24 |
Apr 02 03:09:20 PM PDT 24 |
689695680150 ps |
| T818 |
/workspace/coverage/default/43.sram_ctrl_access_during_key_req.1707494155 |
|
|
Apr 02 02:40:17 PM PDT 24 |
Apr 02 02:55:33 PM PDT 24 |
9191257571 ps |
| T819 |
/workspace/coverage/default/1.sram_ctrl_lc_escalation.3721959512 |
|
|
Apr 02 02:26:56 PM PDT 24 |
Apr 02 02:27:13 PM PDT 24 |
9535296871 ps |
| T820 |
/workspace/coverage/default/25.sram_ctrl_smoke.1297044323 |
|
|
Apr 02 02:34:01 PM PDT 24 |
Apr 02 02:34:20 PM PDT 24 |
5098185282 ps |
| T821 |
/workspace/coverage/default/33.sram_ctrl_stress_all.1439590081 |
|
|
Apr 02 02:37:41 PM PDT 24 |
Apr 02 04:00:12 PM PDT 24 |
332512913962 ps |
| T822 |
/workspace/coverage/default/38.sram_ctrl_executable.2025780844 |
|
|
Apr 02 02:39:27 PM PDT 24 |
Apr 02 03:13:09 PM PDT 24 |
13274740338 ps |
| T823 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2078224300 |
|
|
Apr 02 02:34:13 PM PDT 24 |
Apr 02 02:34:48 PM PDT 24 |
20660838414 ps |
| T824 |
/workspace/coverage/default/25.sram_ctrl_mem_walk.1331926544 |
|
|
Apr 02 02:34:30 PM PDT 24 |
Apr 02 02:36:47 PM PDT 24 |
28710099607 ps |
| T825 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.2532967221 |
|
|
Apr 02 02:37:00 PM PDT 24 |
Apr 02 02:43:29 PM PDT 24 |
32929374713 ps |
| T826 |
/workspace/coverage/default/10.sram_ctrl_regwen.4228907106 |
|
|
Apr 02 02:29:07 PM PDT 24 |
Apr 02 02:43:38 PM PDT 24 |
2993807836 ps |
| T827 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.2459081934 |
|
|
Apr 02 02:28:30 PM PDT 24 |
Apr 02 02:32:51 PM PDT 24 |
13770193953 ps |
| T828 |
/workspace/coverage/default/48.sram_ctrl_lc_escalation.1587576104 |
|
|
Apr 02 02:41:15 PM PDT 24 |
Apr 02 02:42:01 PM PDT 24 |
21567571209 ps |
| T829 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.3630177904 |
|
|
Apr 02 02:38:30 PM PDT 24 |
Apr 02 02:42:04 PM PDT 24 |
6784379244 ps |
| T830 |
/workspace/coverage/default/7.sram_ctrl_ram_cfg.1648454599 |
|
|
Apr 02 02:28:14 PM PDT 24 |
Apr 02 02:28:18 PM PDT 24 |
690758054 ps |
| T831 |
/workspace/coverage/default/4.sram_ctrl_throughput_w_partial_write.2362602171 |
|
|
Apr 02 02:27:41 PM PDT 24 |
Apr 02 02:28:33 PM PDT 24 |
1748834029 ps |
| T832 |
/workspace/coverage/default/47.sram_ctrl_mem_partial_access.1642514404 |
|
|
Apr 02 02:41:10 PM PDT 24 |
Apr 02 02:42:11 PM PDT 24 |
996989512 ps |
| T833 |
/workspace/coverage/default/20.sram_ctrl_executable.2331421814 |
|
|
Apr 02 02:32:26 PM PDT 24 |
Apr 02 02:51:24 PM PDT 24 |
65544263956 ps |
| T834 |
/workspace/coverage/default/46.sram_ctrl_stress_all_with_rand_reset.2102877782 |
|
|
Apr 02 02:41:00 PM PDT 24 |
Apr 02 02:44:00 PM PDT 24 |
4609271173 ps |
| T835 |
/workspace/coverage/default/0.sram_ctrl_mem_walk.1149325919 |
|
|
Apr 02 02:26:45 PM PDT 24 |
Apr 02 02:30:38 PM PDT 24 |
3954181840 ps |
| T836 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1606915317 |
|
|
Apr 02 02:41:00 PM PDT 24 |
Apr 02 02:43:19 PM PDT 24 |
18076399445 ps |
| T837 |
/workspace/coverage/default/14.sram_ctrl_partial_access.3246581883 |
|
|
Apr 02 02:30:04 PM PDT 24 |
Apr 02 02:30:09 PM PDT 24 |
1794084703 ps |
| T42 |
/workspace/coverage/default/3.sram_ctrl_sec_cm.296717396 |
|
|
Apr 02 02:27:30 PM PDT 24 |
Apr 02 02:27:32 PM PDT 24 |
574096609 ps |
| T838 |
/workspace/coverage/default/0.sram_ctrl_access_during_key_req.2270643675 |
|
|
Apr 02 02:26:46 PM PDT 24 |
Apr 02 02:38:43 PM PDT 24 |
47258456004 ps |
| T839 |
/workspace/coverage/default/0.sram_ctrl_executable.727574322 |
|
|
Apr 02 02:26:45 PM PDT 24 |
Apr 02 02:33:31 PM PDT 24 |
10392873008 ps |
| T840 |
/workspace/coverage/default/0.sram_ctrl_smoke.1824479031 |
|
|
Apr 02 02:26:40 PM PDT 24 |
Apr 02 02:26:47 PM PDT 24 |
1417322271 ps |
| T841 |
/workspace/coverage/default/41.sram_ctrl_alert_test.1658975630 |
|
|
Apr 02 02:40:07 PM PDT 24 |
Apr 02 02:40:08 PM PDT 24 |
66509991 ps |
| T842 |
/workspace/coverage/default/31.sram_ctrl_regwen.1828402911 |
|
|
Apr 02 02:36:39 PM PDT 24 |
Apr 02 02:47:20 PM PDT 24 |
10944389982 ps |
| T843 |
/workspace/coverage/default/41.sram_ctrl_mem_walk.3665377244 |
|
|
Apr 02 02:39:58 PM PDT 24 |
Apr 02 02:42:34 PM PDT 24 |
38231493015 ps |
| T844 |
/workspace/coverage/default/35.sram_ctrl_bijection.3654938111 |
|
|
Apr 02 02:37:59 PM PDT 24 |
Apr 02 03:12:18 PM PDT 24 |
488901652576 ps |
| T845 |
/workspace/coverage/default/10.sram_ctrl_max_throughput.2956865588 |
|
|
Apr 02 02:29:02 PM PDT 24 |
Apr 02 02:29:15 PM PDT 24 |
1461906102 ps |
| T846 |
/workspace/coverage/default/30.sram_ctrl_bijection.208044963 |
|
|
Apr 02 02:36:16 PM PDT 24 |
Apr 02 03:10:01 PM PDT 24 |
113679637380 ps |
| T847 |
/workspace/coverage/default/8.sram_ctrl_multiple_keys.4227632848 |
|
|
Apr 02 02:28:21 PM PDT 24 |
Apr 02 02:48:08 PM PDT 24 |
129250577910 ps |
| T848 |
/workspace/coverage/default/32.sram_ctrl_partial_access.3712360004 |
|
|
Apr 02 02:36:57 PM PDT 24 |
Apr 02 02:38:51 PM PDT 24 |
851608774 ps |
| T849 |
/workspace/coverage/default/34.sram_ctrl_stress_all_with_rand_reset.3966365756 |
|
|
Apr 02 02:37:56 PM PDT 24 |
Apr 02 02:39:18 PM PDT 24 |
2424807055 ps |
| T850 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2792463942 |
|
|
Apr 02 02:32:22 PM PDT 24 |
Apr 02 02:32:49 PM PDT 24 |
1603540494 ps |
| T851 |
/workspace/coverage/default/41.sram_ctrl_multiple_keys.4023192674 |
|
|
Apr 02 02:39:56 PM PDT 24 |
Apr 02 03:16:19 PM PDT 24 |
78256121872 ps |
| T852 |
/workspace/coverage/default/21.sram_ctrl_max_throughput.3795844592 |
|
|
Apr 02 02:32:43 PM PDT 24 |
Apr 02 02:32:59 PM PDT 24 |
1460551253 ps |
| T853 |
/workspace/coverage/default/49.sram_ctrl_alert_test.4210221847 |
|
|
Apr 02 02:41:34 PM PDT 24 |
Apr 02 02:41:34 PM PDT 24 |
13199715 ps |
| T854 |
/workspace/coverage/default/39.sram_ctrl_access_during_key_req.3087298931 |
|
|
Apr 02 02:39:36 PM PDT 24 |
Apr 02 02:42:38 PM PDT 24 |
1984326176 ps |
| T855 |
/workspace/coverage/default/18.sram_ctrl_multiple_keys.1890237979 |
|
|
Apr 02 02:31:22 PM PDT 24 |
Apr 02 02:49:01 PM PDT 24 |
9251546453 ps |
| T856 |
/workspace/coverage/default/1.sram_ctrl_stress_all.2089191220 |
|
|
Apr 02 02:27:07 PM PDT 24 |
Apr 02 03:15:01 PM PDT 24 |
111771439415 ps |
| T857 |
/workspace/coverage/default/41.sram_ctrl_bijection.3123886269 |
|
|
Apr 02 02:39:56 PM PDT 24 |
Apr 02 03:24:54 PM PDT 24 |
632380162347 ps |
| T858 |
/workspace/coverage/default/35.sram_ctrl_stress_all_with_rand_reset.1933431174 |
|
|
Apr 02 02:38:24 PM PDT 24 |
Apr 02 02:39:00 PM PDT 24 |
1476719648 ps |
| T859 |
/workspace/coverage/default/37.sram_ctrl_lc_escalation.990500580 |
|
|
Apr 02 02:39:10 PM PDT 24 |
Apr 02 02:39:59 PM PDT 24 |
17199916302 ps |
| T860 |
/workspace/coverage/default/1.sram_ctrl_access_during_key_req.3385629355 |
|
|
Apr 02 02:26:59 PM PDT 24 |
Apr 02 02:37:50 PM PDT 24 |
46598063947 ps |
| T861 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.3405158899 |
|
|
Apr 02 02:27:17 PM PDT 24 |
Apr 02 02:28:36 PM PDT 24 |
2505679441 ps |
| T862 |
/workspace/coverage/default/37.sram_ctrl_partial_access_b2b.1722904005 |
|
|
Apr 02 02:38:58 PM PDT 24 |
Apr 02 02:44:07 PM PDT 24 |
19633577957 ps |
| T863 |
/workspace/coverage/default/5.sram_ctrl_access_during_key_req.655933194 |
|
|
Apr 02 02:27:46 PM PDT 24 |
Apr 02 02:34:17 PM PDT 24 |
7337959521 ps |
| T864 |
/workspace/coverage/default/38.sram_ctrl_lc_escalation.154256301 |
|
|
Apr 02 02:39:24 PM PDT 24 |
Apr 02 02:40:06 PM PDT 24 |
23452150176 ps |
| T865 |
/workspace/coverage/default/29.sram_ctrl_bijection.4008091508 |
|
|
Apr 02 02:35:51 PM PDT 24 |
Apr 02 02:54:33 PM PDT 24 |
71327521360 ps |
| T866 |
/workspace/coverage/default/35.sram_ctrl_smoke.2952883926 |
|
|
Apr 02 02:37:55 PM PDT 24 |
Apr 02 02:37:59 PM PDT 24 |
1501016621 ps |
| T867 |
/workspace/coverage/default/18.sram_ctrl_alert_test.2706234587 |
|
|
Apr 02 02:31:47 PM PDT 24 |
Apr 02 02:31:47 PM PDT 24 |
41248160 ps |
| T868 |
/workspace/coverage/default/34.sram_ctrl_lc_escalation.326721505 |
|
|
Apr 02 02:37:49 PM PDT 24 |
Apr 02 02:38:58 PM PDT 24 |
10730426769 ps |
| T869 |
/workspace/coverage/default/15.sram_ctrl_stress_all.2955925783 |
|
|
Apr 02 02:30:33 PM PDT 24 |
Apr 02 04:22:39 PM PDT 24 |
549488877865 ps |
| T870 |
/workspace/coverage/default/4.sram_ctrl_lc_escalation.73206900 |
|
|
Apr 02 02:27:38 PM PDT 24 |
Apr 02 02:28:31 PM PDT 24 |
8617786081 ps |
| T871 |
/workspace/coverage/default/1.sram_ctrl_partial_access.1105672503 |
|
|
Apr 02 02:27:00 PM PDT 24 |
Apr 02 02:27:11 PM PDT 24 |
2044648431 ps |
| T872 |
/workspace/coverage/default/12.sram_ctrl_smoke.386819201 |
|
|
Apr 02 02:29:29 PM PDT 24 |
Apr 02 02:31:09 PM PDT 24 |
6356435040 ps |
| T873 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.3629547237 |
|
|
Apr 02 02:27:13 PM PDT 24 |
Apr 02 02:37:11 PM PDT 24 |
7884221159 ps |
| T874 |
/workspace/coverage/default/2.sram_ctrl_alert_test.924920411 |
|
|
Apr 02 02:27:23 PM PDT 24 |
Apr 02 02:27:24 PM PDT 24 |
16393130 ps |
| T875 |
/workspace/coverage/default/19.sram_ctrl_stress_pipeline.1577118719 |
|
|
Apr 02 02:31:49 PM PDT 24 |
Apr 02 02:35:56 PM PDT 24 |
4109919442 ps |
| T876 |
/workspace/coverage/default/22.sram_ctrl_stress_all_with_rand_reset.3352346364 |
|
|
Apr 02 02:33:14 PM PDT 24 |
Apr 02 02:34:34 PM PDT 24 |
1313959548 ps |
| T877 |
/workspace/coverage/default/48.sram_ctrl_alert_test.3950638477 |
|
|
Apr 02 02:41:23 PM PDT 24 |
Apr 02 02:41:24 PM PDT 24 |
13305599 ps |
| T878 |
/workspace/coverage/default/32.sram_ctrl_executable.3297458063 |
|
|
Apr 02 02:37:02 PM PDT 24 |
Apr 02 02:40:16 PM PDT 24 |
9573752003 ps |
| T879 |
/workspace/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.1671473618 |
|
|
Apr 02 02:26:49 PM PDT 24 |
Apr 02 02:26:58 PM PDT 24 |
455050954 ps |
| T880 |
/workspace/coverage/default/16.sram_ctrl_stress_pipeline.3213456609 |
|
|
Apr 02 02:30:43 PM PDT 24 |
Apr 02 02:36:19 PM PDT 24 |
5276027274 ps |
| T881 |
/workspace/coverage/default/30.sram_ctrl_multiple_keys.3914444519 |
|
|
Apr 02 02:36:17 PM PDT 24 |
Apr 02 02:41:46 PM PDT 24 |
9733737695 ps |
| T882 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.128558089 |
|
|
Apr 02 02:36:26 PM PDT 24 |
Apr 02 02:39:39 PM PDT 24 |
7202975770 ps |
| T883 |
/workspace/coverage/default/28.sram_ctrl_stress_all_with_rand_reset.917428712 |
|
|
Apr 02 02:35:43 PM PDT 24 |
Apr 02 02:35:54 PM PDT 24 |
649463868 ps |
| T884 |
/workspace/coverage/default/41.sram_ctrl_regwen.3009192721 |
|
|
Apr 02 02:40:04 PM PDT 24 |
Apr 02 02:49:45 PM PDT 24 |
4186828178 ps |
| T885 |
/workspace/coverage/default/11.sram_ctrl_ram_cfg.2095713534 |
|
|
Apr 02 02:29:24 PM PDT 24 |
Apr 02 02:29:27 PM PDT 24 |
656512547 ps |
| T886 |
/workspace/coverage/default/0.sram_ctrl_lc_escalation.2942045664 |
|
|
Apr 02 02:26:42 PM PDT 24 |
Apr 02 02:26:52 PM PDT 24 |
3689804216 ps |
| T887 |
/workspace/coverage/default/0.sram_ctrl_regwen.820011022 |
|
|
Apr 02 02:26:52 PM PDT 24 |
Apr 02 02:32:22 PM PDT 24 |
30299509775 ps |
| T888 |
/workspace/coverage/default/9.sram_ctrl_executable.1390717970 |
|
|
Apr 02 02:28:46 PM PDT 24 |
Apr 02 02:50:20 PM PDT 24 |
89787559742 ps |
| T889 |
/workspace/coverage/default/10.sram_ctrl_mem_partial_access.581628379 |
|
|
Apr 02 02:29:07 PM PDT 24 |
Apr 02 02:30:20 PM PDT 24 |
2552596295 ps |
| T890 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.1788164426 |
|
|
Apr 02 02:36:48 PM PDT 24 |
Apr 02 02:40:38 PM PDT 24 |
28727713402 ps |
| T891 |
/workspace/coverage/default/21.sram_ctrl_access_during_key_req.1036856363 |
|
|
Apr 02 02:32:44 PM PDT 24 |
Apr 02 02:39:47 PM PDT 24 |
75732829151 ps |
| T892 |
/workspace/coverage/default/31.sram_ctrl_throughput_w_partial_write.1655438493 |
|
|
Apr 02 02:36:30 PM PDT 24 |
Apr 02 02:38:21 PM PDT 24 |
811666098 ps |
| T893 |
/workspace/coverage/default/11.sram_ctrl_smoke.1383366700 |
|
|
Apr 02 02:29:08 PM PDT 24 |
Apr 02 02:29:28 PM PDT 24 |
4751090728 ps |
| T894 |
/workspace/coverage/default/35.sram_ctrl_throughput_w_partial_write.1704499452 |
|
|
Apr 02 02:38:15 PM PDT 24 |
Apr 02 02:39:05 PM PDT 24 |
1546916458 ps |
| T895 |
/workspace/coverage/default/20.sram_ctrl_stress_all_with_rand_reset.2728969391 |
|
|
Apr 02 02:32:28 PM PDT 24 |
Apr 02 02:33:38 PM PDT 24 |
3707728757 ps |
| T896 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.393965329 |
|
|
Apr 02 02:27:40 PM PDT 24 |
Apr 02 02:34:10 PM PDT 24 |
11839173143 ps |
| T897 |
/workspace/coverage/default/4.sram_ctrl_bijection.1586318748 |
|
|
Apr 02 02:27:35 PM PDT 24 |
Apr 02 03:01:07 PM PDT 24 |
678523977755 ps |
| T898 |
/workspace/coverage/default/3.sram_ctrl_mem_partial_access.3472156743 |
|
|
Apr 02 02:27:28 PM PDT 24 |
Apr 02 02:29:25 PM PDT 24 |
6204144479 ps |
| T899 |
/workspace/coverage/default/5.sram_ctrl_executable.2927163769 |
|
|
Apr 02 02:27:50 PM PDT 24 |
Apr 02 02:40:27 PM PDT 24 |
7349674911 ps |
| T900 |
/workspace/coverage/default/27.sram_ctrl_bijection.2670796506 |
|
|
Apr 02 02:35:10 PM PDT 24 |
Apr 02 02:56:02 PM PDT 24 |
317864847467 ps |
| T901 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3469025052 |
|
|
Apr 02 02:31:19 PM PDT 24 |
Apr 02 02:31:20 PM PDT 24 |
38374258 ps |
| T902 |
/workspace/coverage/default/3.sram_ctrl_smoke.1966563173 |
|
|
Apr 02 02:27:21 PM PDT 24 |
Apr 02 02:28:57 PM PDT 24 |
3219856701 ps |
| T903 |
/workspace/coverage/default/46.sram_ctrl_regwen.747326865 |
|
|
Apr 02 02:41:01 PM PDT 24 |
Apr 02 02:57:51 PM PDT 24 |
11793965511 ps |
| T904 |
/workspace/coverage/default/10.sram_ctrl_stress_all_with_rand_reset.214023488 |
|
|
Apr 02 02:29:04 PM PDT 24 |
Apr 02 02:29:53 PM PDT 24 |
1874909950 ps |
| T905 |
/workspace/coverage/default/42.sram_ctrl_throughput_w_partial_write.3398419451 |
|
|
Apr 02 02:40:16 PM PDT 24 |
Apr 02 02:40:41 PM PDT 24 |
2988615894 ps |
| T906 |
/workspace/coverage/default/31.sram_ctrl_stress_all_with_rand_reset.848659538 |
|
|
Apr 02 02:36:46 PM PDT 24 |
Apr 02 02:38:12 PM PDT 24 |
2613821823 ps |
| T907 |
/workspace/coverage/default/41.sram_ctrl_executable.748137552 |
|
|
Apr 02 02:39:56 PM PDT 24 |
Apr 02 03:20:40 PM PDT 24 |
46684425773 ps |
| T908 |
/workspace/coverage/default/47.sram_ctrl_stress_all.1457351729 |
|
|
Apr 02 02:41:13 PM PDT 24 |
Apr 02 03:30:10 PM PDT 24 |
49334549430 ps |
| T909 |
/workspace/coverage/default/41.sram_ctrl_mem_partial_access.1228911633 |
|
|
Apr 02 02:39:59 PM PDT 24 |
Apr 02 02:41:16 PM PDT 24 |
2423831742 ps |
| T910 |
/workspace/coverage/default/19.sram_ctrl_alert_test.1881856789 |
|
|
Apr 02 02:32:14 PM PDT 24 |
Apr 02 02:32:14 PM PDT 24 |
15226380 ps |
| T911 |
/workspace/coverage/default/39.sram_ctrl_throughput_w_partial_write.2964687251 |
|
|
Apr 02 02:39:35 PM PDT 24 |
Apr 02 02:40:18 PM PDT 24 |
8280382626 ps |
| T912 |
/workspace/coverage/default/12.sram_ctrl_executable.1967949730 |
|
|
Apr 02 02:29:36 PM PDT 24 |
Apr 02 02:45:44 PM PDT 24 |
43533974159 ps |
| T913 |
/workspace/coverage/default/30.sram_ctrl_mem_walk.86751205 |
|
|
Apr 02 02:36:23 PM PDT 24 |
Apr 02 02:40:35 PM PDT 24 |
3984774437 ps |
| T914 |
/workspace/coverage/default/43.sram_ctrl_stress_all_with_rand_reset.1825167881 |
|
|
Apr 02 02:40:22 PM PDT 24 |
Apr 02 02:40:43 PM PDT 24 |
1120039492 ps |
| T915 |
/workspace/coverage/default/26.sram_ctrl_lc_escalation.4018320432 |
|
|
Apr 02 02:34:49 PM PDT 24 |
Apr 02 02:35:51 PM PDT 24 |
11415159745 ps |
| T916 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.2444947979 |
|
|
Apr 02 02:38:13 PM PDT 24 |
Apr 02 02:38:58 PM PDT 24 |
11863282272 ps |
| T917 |
/workspace/coverage/default/25.sram_ctrl_executable.906607689 |
|
|
Apr 02 02:34:14 PM PDT 24 |
Apr 02 02:50:50 PM PDT 24 |
8368932866 ps |
| T918 |
/workspace/coverage/default/10.sram_ctrl_lc_escalation.2758869052 |
|
|
Apr 02 02:29:03 PM PDT 24 |
Apr 02 02:29:44 PM PDT 24 |
7804929624 ps |
| T919 |
/workspace/coverage/default/35.sram_ctrl_ram_cfg.58284790 |
|
|
Apr 02 02:38:16 PM PDT 24 |
Apr 02 02:38:20 PM PDT 24 |
679494136 ps |
| T920 |
/workspace/coverage/default/22.sram_ctrl_stress_pipeline.4099882829 |
|
|
Apr 02 02:33:01 PM PDT 24 |
Apr 02 02:37:43 PM PDT 24 |
8713437664 ps |
| T921 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3174533677 |
|
|
Apr 02 02:39:17 PM PDT 24 |
Apr 02 03:05:39 PM PDT 24 |
11457054108 ps |
| T922 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.2502120385 |
|
|
Apr 02 02:35:29 PM PDT 24 |
Apr 02 02:43:06 PM PDT 24 |
56042795136 ps |
| T923 |
/workspace/coverage/default/11.sram_ctrl_partial_access_b2b.2747374850 |
|
|
Apr 02 02:29:13 PM PDT 24 |
Apr 02 02:34:57 PM PDT 24 |
134160669240 ps |
| T924 |
/workspace/coverage/default/6.sram_ctrl_stress_pipeline.2535510000 |
|
|
Apr 02 02:27:53 PM PDT 24 |
Apr 02 02:34:31 PM PDT 24 |
6797006604 ps |
| T925 |
/workspace/coverage/default/16.sram_ctrl_stress_all.2063637562 |
|
|
Apr 02 02:30:55 PM PDT 24 |
Apr 02 03:55:31 PM PDT 24 |
123141142150 ps |
| T926 |
/workspace/coverage/default/12.sram_ctrl_mem_walk.4003369699 |
|
|
Apr 02 02:29:34 PM PDT 24 |
Apr 02 02:34:24 PM PDT 24 |
42139083179 ps |
| T927 |
/workspace/coverage/default/35.sram_ctrl_stress_all.1634243272 |
|
|
Apr 02 02:38:20 PM PDT 24 |
Apr 02 03:55:37 PM PDT 24 |
55723905760 ps |
| T928 |
/workspace/coverage/default/20.sram_ctrl_mem_partial_access.790562441 |
|
|
Apr 02 02:32:28 PM PDT 24 |
Apr 02 02:33:30 PM PDT 24 |
3771768664 ps |
| T929 |
/workspace/coverage/default/40.sram_ctrl_multiple_keys.3209050420 |
|
|
Apr 02 02:39:43 PM PDT 24 |
Apr 02 02:56:57 PM PDT 24 |
10854483971 ps |
| T930 |
/workspace/coverage/default/8.sram_ctrl_ram_cfg.2549471614 |
|
|
Apr 02 02:28:29 PM PDT 24 |
Apr 02 02:28:33 PM PDT 24 |
360531224 ps |
| T931 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.4163766768 |
|
|
Apr 02 02:39:01 PM PDT 24 |
Apr 02 03:07:40 PM PDT 24 |
51815544630 ps |
| T932 |
/workspace/coverage/default/37.sram_ctrl_throughput_w_partial_write.3035535565 |
|
|
Apr 02 02:39:03 PM PDT 24 |
Apr 02 02:39:18 PM PDT 24 |
2922879900 ps |
| T933 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.4194668480 |
|
|
Apr 02 02:33:27 PM PDT 24 |
Apr 02 02:33:31 PM PDT 24 |
706091832 ps |
| T934 |
/workspace/coverage/default/34.sram_ctrl_smoke.1516466613 |
|
|
Apr 02 02:37:44 PM PDT 24 |
Apr 02 02:37:50 PM PDT 24 |
2310701481 ps |
| T935 |
/workspace/coverage/default/45.sram_ctrl_lc_escalation.2314583918 |
|
|
Apr 02 02:40:44 PM PDT 24 |
Apr 02 02:41:12 PM PDT 24 |
4809264709 ps |
| T936 |
/workspace/coverage/default/48.sram_ctrl_ram_cfg.941239466 |
|
|
Apr 02 02:41:23 PM PDT 24 |
Apr 02 02:41:27 PM PDT 24 |
656201831 ps |
| T937 |
/workspace/coverage/default/34.sram_ctrl_executable.2301819348 |
|
|
Apr 02 02:37:50 PM PDT 24 |
Apr 02 02:57:06 PM PDT 24 |
106179831261 ps |
| T938 |
/workspace/coverage/default/3.sram_ctrl_stress_pipeline.3615751176 |
|
|
Apr 02 02:27:22 PM PDT 24 |
Apr 02 02:31:49 PM PDT 24 |
5117383439 ps |
| T939 |
/workspace/coverage/default/47.sram_ctrl_throughput_w_partial_write.878335015 |
|
|
Apr 02 02:41:09 PM PDT 24 |
Apr 02 02:42:04 PM PDT 24 |
2980991678 ps |
| T940 |
/workspace/coverage/default/38.sram_ctrl_access_during_key_req.1615343732 |
|
|
Apr 02 02:39:28 PM PDT 24 |
Apr 02 02:50:44 PM PDT 24 |
40925576966 ps |
| T85 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.2875524061 |
|
|
Apr 02 12:30:12 PM PDT 24 |
Apr 02 12:31:02 PM PDT 24 |
7434757699 ps |
| T86 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_same_csr_outstanding.1868955311 |
|
|
Apr 02 12:30:24 PM PDT 24 |
Apr 02 12:30:25 PM PDT 24 |
14732822 ps |
| T60 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_passthru_mem_tl_intg_err.1827544671 |
|
|
Apr 02 12:29:59 PM PDT 24 |
Apr 02 12:30:31 PM PDT 24 |
28435285124 ps |
| T941 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1791910763 |
|
|
Apr 02 12:30:10 PM PDT 24 |
Apr 02 12:30:12 PM PDT 24 |
60873351 ps |
| T87 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.1510557057 |
|
|
Apr 02 12:30:28 PM PDT 24 |
Apr 02 12:30:29 PM PDT 24 |
44132221 ps |
| T942 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1282673561 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:18 PM PDT 24 |
524735590 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.609592453 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:30:28 PM PDT 24 |
26054552 ps |
| T61 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.2910653913 |
|
|
Apr 02 12:30:32 PM PDT 24 |
Apr 02 12:31:21 PM PDT 24 |
7285273813 ps |
| T93 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3552654060 |
|
|
Apr 02 12:29:53 PM PDT 24 |
Apr 02 12:29:54 PM PDT 24 |
50226157 ps |
| T943 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.3684676747 |
|
|
Apr 02 12:29:53 PM PDT 24 |
Apr 02 12:29:54 PM PDT 24 |
44294934 ps |
| T95 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2842888501 |
|
|
Apr 02 12:29:46 PM PDT 24 |
Apr 02 12:29:49 PM PDT 24 |
862507290 ps |
| T62 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2120853622 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:14 PM PDT 24 |
13729100 ps |
| T63 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_passthru_mem_tl_intg_err.1888486655 |
|
|
Apr 02 12:30:16 PM PDT 24 |
Apr 02 12:31:06 PM PDT 24 |
13827546773 ps |
| T944 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3651087056 |
|
|
Apr 02 12:29:54 PM PDT 24 |
Apr 02 12:29:56 PM PDT 24 |
227367462 ps |
| T945 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.1389073798 |
|
|
Apr 02 12:29:47 PM PDT 24 |
Apr 02 12:29:51 PM PDT 24 |
544544238 ps |
| T64 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.366476327 |
|
|
Apr 02 12:30:15 PM PDT 24 |
Apr 02 12:30:17 PM PDT 24 |
18751226 ps |
| T946 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1952077137 |
|
|
Apr 02 12:29:51 PM PDT 24 |
Apr 02 12:29:56 PM PDT 24 |
123867969 ps |
| T65 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_rw.3333341838 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:14 PM PDT 24 |
14239629 ps |
| T66 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.536812239 |
|
|
Apr 02 12:30:10 PM PDT 24 |
Apr 02 12:30:35 PM PDT 24 |
3781585267 ps |
| T947 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.285916819 |
|
|
Apr 02 12:30:20 PM PDT 24 |
Apr 02 12:30:25 PM PDT 24 |
1282017922 ps |
| T948 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.3135566070 |
|
|
Apr 02 12:29:52 PM PDT 24 |
Apr 02 12:29:53 PM PDT 24 |
66109200 ps |
| T96 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.1219754596 |
|
|
Apr 02 12:30:26 PM PDT 24 |
Apr 02 12:30:27 PM PDT 24 |
143757034 ps |
| T949 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.1619498583 |
|
|
Apr 02 12:29:50 PM PDT 24 |
Apr 02 12:29:52 PM PDT 24 |
82569671 ps |
| T950 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.812292299 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:30:32 PM PDT 24 |
373587405 ps |
| T67 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.589344878 |
|
|
Apr 02 12:30:10 PM PDT 24 |
Apr 02 12:30:11 PM PDT 24 |
16343238 ps |
| T951 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.788084049 |
|
|
Apr 02 12:29:54 PM PDT 24 |
Apr 02 12:29:58 PM PDT 24 |
339254393 ps |
| T952 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.2828361297 |
|
|
Apr 02 12:30:16 PM PDT 24 |
Apr 02 12:30:19 PM PDT 24 |
74365616 ps |
| T953 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.2393900017 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:30:28 PM PDT 24 |
12183225 ps |
| T68 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.673327429 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:30:27 PM PDT 24 |
33489991 ps |
| T954 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.1843480825 |
|
|
Apr 02 12:30:04 PM PDT 24 |
Apr 02 12:30:08 PM PDT 24 |
358723865 ps |
| T955 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_errors.3148163834 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:16 PM PDT 24 |
271158633 ps |
| T956 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.707634025 |
|
|
Apr 02 12:30:30 PM PDT 24 |
Apr 02 12:30:31 PM PDT 24 |
49305567 ps |
| T957 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3123219471 |
|
|
Apr 02 12:29:42 PM PDT 24 |
Apr 02 12:29:43 PM PDT 24 |
71758154 ps |
| T97 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.3595276048 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:15 PM PDT 24 |
94500875 ps |
| T958 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.1309180998 |
|
|
Apr 02 12:30:32 PM PDT 24 |
Apr 02 12:30:38 PM PDT 24 |
45439880 ps |
| T959 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.3263822438 |
|
|
Apr 02 12:30:14 PM PDT 24 |
Apr 02 12:30:15 PM PDT 24 |
41375621 ps |
| T69 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.2449667886 |
|
|
Apr 02 12:30:24 PM PDT 24 |
Apr 02 12:30:50 PM PDT 24 |
3728086194 ps |
| T106 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1824397527 |
|
|
Apr 02 12:30:21 PM PDT 24 |
Apr 02 12:30:23 PM PDT 24 |
134927902 ps |
| T109 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.1056219857 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:30:29 PM PDT 24 |
254560112 ps |
| T112 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.3055092886 |
|
|
Apr 02 12:30:04 PM PDT 24 |
Apr 02 12:30:06 PM PDT 24 |
176085342 ps |
| T960 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.242562366 |
|
|
Apr 02 12:29:46 PM PDT 24 |
Apr 02 12:29:48 PM PDT 24 |
84309803 ps |
| T110 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1348131648 |
|
|
Apr 02 12:31:08 PM PDT 24 |
Apr 02 12:31:10 PM PDT 24 |
650760878 ps |
| T961 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1794124708 |
|
|
Apr 02 12:30:18 PM PDT 24 |
Apr 02 12:30:22 PM PDT 24 |
1094862538 ps |
| T107 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.324972341 |
|
|
Apr 02 12:30:31 PM PDT 24 |
Apr 02 12:30:34 PM PDT 24 |
222156764 ps |
| T71 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.95669565 |
|
|
Apr 02 12:30:21 PM PDT 24 |
Apr 02 12:31:18 PM PDT 24 |
29290630328 ps |
| T962 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1098250734 |
|
|
Apr 02 12:29:50 PM PDT 24 |
Apr 02 12:29:51 PM PDT 24 |
38350272 ps |
| T963 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.3629634503 |
|
|
Apr 02 12:30:02 PM PDT 24 |
Apr 02 12:30:03 PM PDT 24 |
18019896 ps |
| T964 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_passthru_mem_tl_intg_err.501672341 |
|
|
Apr 02 12:30:28 PM PDT 24 |
Apr 02 12:30:56 PM PDT 24 |
14779531470 ps |
| T965 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_same_csr_outstanding.1701467607 |
|
|
Apr 02 12:30:20 PM PDT 24 |
Apr 02 12:30:20 PM PDT 24 |
43817659 ps |
| T966 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.3967529352 |
|
|
Apr 02 12:30:15 PM PDT 24 |
Apr 02 12:30:17 PM PDT 24 |
46216464 ps |
| T108 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.681526636 |
|
|
Apr 02 12:30:21 PM PDT 24 |
Apr 02 12:30:24 PM PDT 24 |
608827020 ps |
| T967 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.120303238 |
|
|
Apr 02 12:30:17 PM PDT 24 |
Apr 02 12:30:19 PM PDT 24 |
97038967 ps |
| T968 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_rw.3405243902 |
|
|
Apr 02 12:30:34 PM PDT 24 |
Apr 02 12:30:35 PM PDT 24 |
50894722 ps |
| T969 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.2175653742 |
|
|
Apr 02 12:30:29 PM PDT 24 |
Apr 02 12:30:30 PM PDT 24 |
106205263 ps |
| T970 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.3854221747 |
|
|
Apr 02 12:29:44 PM PDT 24 |
Apr 02 12:29:45 PM PDT 24 |
37928986 ps |
| T72 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_passthru_mem_tl_intg_err.2653426721 |
|
|
Apr 02 12:30:17 PM PDT 24 |
Apr 02 12:31:11 PM PDT 24 |
14112289659 ps |
| T971 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.18959860 |
|
|
Apr 02 12:29:53 PM PDT 24 |
Apr 02 12:29:57 PM PDT 24 |
784456294 ps |
| T972 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_errors.1389471857 |
|
|
Apr 02 12:30:31 PM PDT 24 |
Apr 02 12:30:33 PM PDT 24 |
58705106 ps |
| T973 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.3350813691 |
|
|
Apr 02 12:30:31 PM PDT 24 |
Apr 02 12:30:32 PM PDT 24 |
56461435 ps |
| T73 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2365417392 |
|
|
Apr 02 12:30:12 PM PDT 24 |
Apr 02 12:30:39 PM PDT 24 |
7561667893 ps |
| T74 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_passthru_mem_tl_intg_err.1483433558 |
|
|
Apr 02 12:30:18 PM PDT 24 |
Apr 02 12:31:10 PM PDT 24 |
7427070317 ps |
| T974 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.1578778710 |
|
|
Apr 02 12:30:15 PM PDT 24 |
Apr 02 12:30:18 PM PDT 24 |
14436116 ps |
| T975 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.367760528 |
|
|
Apr 02 12:30:20 PM PDT 24 |
Apr 02 12:30:21 PM PDT 24 |
24476690 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.2924247770 |
|
|
Apr 02 12:29:46 PM PDT 24 |
Apr 02 12:29:47 PM PDT 24 |
411452406 ps |
| T977 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1273306008 |
|
|
Apr 02 12:30:24 PM PDT 24 |
Apr 02 12:30:26 PM PDT 24 |
137149060 ps |
| T978 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1817531577 |
|
|
Apr 02 12:29:46 PM PDT 24 |
Apr 02 12:29:47 PM PDT 24 |
43495950 ps |
| T979 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.2944913083 |
|
|
Apr 02 12:30:03 PM PDT 24 |
Apr 02 12:30:06 PM PDT 24 |
72985632 ps |
| T980 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.697355428 |
|
|
Apr 02 12:30:34 PM PDT 24 |
Apr 02 12:30:36 PM PDT 24 |
44510797 ps |
| T981 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.2523700290 |
|
|
Apr 02 12:30:26 PM PDT 24 |
Apr 02 12:30:30 PM PDT 24 |
1395681890 ps |
| T982 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3943408738 |
|
|
Apr 02 12:30:10 PM PDT 24 |
Apr 02 12:30:11 PM PDT 24 |
13287521 ps |
| T983 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.949428122 |
|
|
Apr 02 12:30:21 PM PDT 24 |
Apr 02 12:30:25 PM PDT 24 |
742963505 ps |
| T984 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4157730967 |
|
|
Apr 02 12:30:11 PM PDT 24 |
Apr 02 12:30:15 PM PDT 24 |
132433286 ps |
| T82 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_rw.3414881445 |
|
|
Apr 02 12:30:25 PM PDT 24 |
Apr 02 12:30:26 PM PDT 24 |
12907876 ps |
| T985 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.3399561771 |
|
|
Apr 02 12:29:49 PM PDT 24 |
Apr 02 12:29:50 PM PDT 24 |
15045598 ps |
| T986 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.975285954 |
|
|
Apr 02 12:29:47 PM PDT 24 |
Apr 02 12:29:51 PM PDT 24 |
717231720 ps |
| T83 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_passthru_mem_tl_intg_err.3111591685 |
|
|
Apr 02 12:29:54 PM PDT 24 |
Apr 02 12:30:28 PM PDT 24 |
52826712656 ps |
| T987 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1937324592 |
|
|
Apr 02 12:30:16 PM PDT 24 |
Apr 02 12:30:19 PM PDT 24 |
353891692 ps |
| T988 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.3855382924 |
|
|
Apr 02 12:30:18 PM PDT 24 |
Apr 02 12:30:19 PM PDT 24 |
49844727 ps |
| T989 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.252456102 |
|
|
Apr 02 12:30:17 PM PDT 24 |
Apr 02 12:30:21 PM PDT 24 |
401612758 ps |
| T990 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.1493394082 |
|
|
Apr 02 12:30:28 PM PDT 24 |
Apr 02 12:30:31 PM PDT 24 |
38588414 ps |
| T991 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_same_csr_outstanding.3811661742 |
|
|
Apr 02 12:30:18 PM PDT 24 |
Apr 02 12:30:19 PM PDT 24 |
19158043 ps |
| T992 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_errors.317506423 |
|
|
Apr 02 12:30:11 PM PDT 24 |
Apr 02 12:30:13 PM PDT 24 |
329467601 ps |
| T84 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1305334426 |
|
|
Apr 02 12:30:19 PM PDT 24 |
Apr 02 12:30:47 PM PDT 24 |
10278701410 ps |
| T993 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_rw.912849078 |
|
|
Apr 02 12:30:29 PM PDT 24 |
Apr 02 12:30:30 PM PDT 24 |
47014163 ps |
| T113 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.570430310 |
|
|
Apr 02 12:30:29 PM PDT 24 |
Apr 02 12:30:31 PM PDT 24 |
218890832 ps |
| T994 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.876243845 |
|
|
Apr 02 12:30:13 PM PDT 24 |
Apr 02 12:30:14 PM PDT 24 |
57867232 ps |
| T995 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1653881402 |
|
|
Apr 02 12:29:53 PM PDT 24 |
Apr 02 12:29:56 PM PDT 24 |
1713926162 ps |
| T996 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_same_csr_outstanding.3712895182 |
|
|
Apr 02 12:30:11 PM PDT 24 |
Apr 02 12:30:12 PM PDT 24 |
38036402 ps |
| T115 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.689762945 |
|
|
Apr 02 12:30:20 PM PDT 24 |
Apr 02 12:30:23 PM PDT 24 |
615145395 ps |
| T111 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.689329907 |
|
|
Apr 02 12:30:33 PM PDT 24 |
Apr 02 12:30:40 PM PDT 24 |
193892292 ps |
| T997 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.311532049 |
|
|
Apr 02 12:30:15 PM PDT 24 |
Apr 02 12:30:16 PM PDT 24 |
54269871 ps |
| T998 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_errors.4193628216 |
|
|
Apr 02 12:30:20 PM PDT 24 |
Apr 02 12:30:24 PM PDT 24 |
209165262 ps |
| T999 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_mem_rw_with_rand_reset.2277064799 |
|
|
Apr 02 12:30:22 PM PDT 24 |
Apr 02 12:30:26 PM PDT 24 |
365286345 ps |
| T1000 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3033228963 |
|
|
Apr 02 12:30:02 PM PDT 24 |
Apr 02 12:30:07 PM PDT 24 |
2293387477 ps |
| T116 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.236261282 |
|
|
Apr 02 12:30:24 PM PDT 24 |
Apr 02 12:30:26 PM PDT 24 |
243735853 ps |
| T1001 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.2492335823 |
|
|
Apr 02 12:30:27 PM PDT 24 |
Apr 02 12:31:18 PM PDT 24 |
14409132759 ps |