Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16770333	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

167446121

1

T1

115472

T2

74597

T4

128421

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	90810483	1			T1	63816		T2	40984		T4	70583
values[0x0]	45034008	1			T1	30424		T2	19867		T4	33975
values[0x1]	48371963	1			T1	32924		T2	21198		T4	36730

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8529777	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

175686677

1

T1

121389

T2

78369

T4

134928

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	571664	1			T1	485		T2	397		T5	449
valid_sources[0x01]	562564	1			T1	465		T2	272		T5	419
valid_sources[0x02]	579876	1			T1	509		T2	362		T5	367
valid_sources[0x03]	596574	1			T1	491		T2	305		T5	329
valid_sources[0x04]	560724	1			T1	511		T2	300		T5	442
valid_sources[0x05]	574050	1			T1	509		T2	246		T5	344
valid_sources[0x06]	587685	1			T1	487		T2	359		T5	379
valid_sources[0x07]	622880	1			T1	517		T2	277		T5	380
valid_sources[0x08]	572621	1			T1	555		T2	305		T5	385
valid_sources[0x09]	659990	1			T1	475		T2	244		T5	380
valid_sources[0x0a]	596966	1			T1	509		T2	386		T5	435
valid_sources[0x0b]	2158575	1			T1	481		T2	307		T5	410
valid_sources[0x0c]	649584	1			T1	492		T2	292		T5	365
valid_sources[0x0d]	2023466	1			T1	521		T2	214		T5	332
valid_sources[0x0e]	636577	1			T1	567		T2	334		T4	37933
valid_sources[0x0f]	569790	1			T1	484		T2	256		T4	2253
valid_sources[0x10]	631930	1			T1	469		T2	286		T5	426
valid_sources[0x11]	1347452	1			T1	476		T2	326		T5	427
valid_sources[0x12]	641168	1			T1	473		T2	318		T5	365
valid_sources[0x13]	573165	1			T1	490		T2	397		T5	340
valid_sources[0x14]	617011	1			T1	556		T2	296		T5	367
valid_sources[0x15]	572198	1			T1	505		T2	313		T5	378
valid_sources[0x16]	583176	1			T1	487		T2	187		T5	366
valid_sources[0x17]	562620	1			T1	496		T2	366		T5	332
valid_sources[0x18]	601113	1			T1	474		T2	350		T5	340
valid_sources[0x19]	577382	1			T1	505		T2	273		T5	386
valid_sources[0x1a]	572212	1			T1	510		T2	235		T5	381
valid_sources[0x1b]	599049	1			T1	490		T2	325		T5	395
valid_sources[0x1c]	597303	1			T1	535		T2	303		T5	393
valid_sources[0x1d]	562503	1			T1	470		T2	305		T5	362
valid_sources[0x1e]	565065	1			T1	525		T2	254		T5	376
valid_sources[0x1f]	1381657	1			T1	496		T2	314		T5	300
valid_sources[0x20]	591346	1			T1	486		T2	324		T5	311
valid_sources[0x21]	1370497	1			T1	495		T2	334		T5	445
valid_sources[0x22]	596663	1			T1	488		T2	386		T4	20872
valid_sources[0x23]	615056	1			T1	490		T2	418		T5	378
valid_sources[0x24]	571040	1			T1	527		T2	256		T5	333
valid_sources[0x25]	578927	1			T1	502		T2	203		T5	350
valid_sources[0x26]	602748	1			T1	462		T2	374		T4	3682
valid_sources[0x27]	576452	1			T1	501		T2	317		T5	369
valid_sources[0x28]	573222	1			T1	489		T2	340		T5	344
valid_sources[0x29]	635801	1			T1	528		T2	404		T5	348
valid_sources[0x2a]	567468	1			T1	481		T2	512		T5	417
valid_sources[0x2b]	650641	1			T1	487		T2	387		T5	374
valid_sources[0x2c]	612340	1			T1	519		T2	209		T5	400
valid_sources[0x2d]	650805	1			T1	600		T2	210		T5	403
valid_sources[0x2e]	582318	1			T1	460		T2	354		T5	355
valid_sources[0x2f]	1135522	1			T1	454		T2	263		T5	371
valid_sources[0x30]	564619	1			T1	512		T2	361		T5	384
valid_sources[0x31]	569433	1			T1	488		T2	277		T5	448
valid_sources[0x32]	2384565	1			T1	513		T2	191		T5	371
valid_sources[0x33]	623205	1			T1	509		T2	306		T5	402
valid_sources[0x34]	599816	1			T1	483		T2	348		T5	413
valid_sources[0x35]	601776	1			T1	536		T2	293		T5	342
valid_sources[0x36]	2049902	1			T1	469		T2	368		T5	399
valid_sources[0x37]	568765	1			T1	481		T2	261		T5	384
valid_sources[0x38]	605429	1			T1	488		T2	250		T5	372
valid_sources[0x39]	605531	1			T1	492		T2	333		T5	459
valid_sources[0x3a]	614550	1			T1	497		T2	307		T5	411
valid_sources[0x3b]	597460	1			T1	484		T2	290		T5	362
valid_sources[0x3c]	590694	1			T1	464		T2	321		T5	361
valid_sources[0x3d]	598119	1			T1	502		T2	372		T5	393
valid_sources[0x3e]	633568	1			T1	505		T2	302		T5	445
valid_sources[0x3f]	1744162	1			T1	477		T2	261		T5	339
valid_sources[0x40]	579153	1			T1	557		T2	400		T5	381
valid_sources[0x41]	588076	1			T1	467		T2	388		T5	425
valid_sources[0x42]	594372	1			T1	484		T2	306		T5	376
valid_sources[0x43]	584587	1			T1	468		T2	465		T5	450
valid_sources[0x44]	2180610	1			T1	463		T2	343		T5	389
valid_sources[0x45]	577039	1			T1	481		T2	395		T5	382
valid_sources[0x46]	573123	1			T1	506		T2	330		T5	375
valid_sources[0x47]	589085	1			T1	491		T2	267		T5	415
valid_sources[0x48]	605121	1			T1	455		T2	292		T5	445
valid_sources[0x49]	628635	1			T1	508		T2	336		T5	402
valid_sources[0x4a]	1727449	1			T1	470		T2	272		T5	386
valid_sources[0x4b]	709910	1			T1	486		T2	353		T5	311
valid_sources[0x4c]	566918	1			T1	539		T2	220		T5	420
valid_sources[0x4d]	790828	1			T1	527		T2	341		T5	365
valid_sources[0x4e]	569351	1			T1	459		T2	442		T5	384
valid_sources[0x4f]	629708	1			T1	457		T2	374		T5	382
valid_sources[0x50]	661784	1			T1	488		T2	295		T5	437
valid_sources[0x51]	611329	1			T1	460		T2	312		T5	435
valid_sources[0x52]	600091	1			T1	541		T2	297		T5	392
valid_sources[0x53]	599797	1			T1	516		T2	310		T5	399
valid_sources[0x54]	572981	1			T1	503		T2	308		T5	429
valid_sources[0x55]	564563	1			T1	487		T2	299		T5	384
valid_sources[0x56]	671505	1			T1	483		T2	416		T5	390
valid_sources[0x57]	589502	1			T1	488		T2	399		T5	367
valid_sources[0x58]	571048	1			T1	465		T2	365		T5	379
valid_sources[0x59]	626809	1			T1	485		T2	331		T5	412
valid_sources[0x5a]	591001	1			T1	489		T2	461		T5	385
valid_sources[0x5b]	2253763	1			T1	461		T2	266		T5	391
valid_sources[0x5c]	586359	1			T1	520		T2	236		T5	380
valid_sources[0x5d]	582070	1			T1	446		T2	259		T5	322
valid_sources[0x5e]	721642	1			T1	504		T2	309		T5	348
valid_sources[0x5f]	2269211	1			T1	512		T2	362		T5	414
valid_sources[0x60]	591358	1			T1	517		T2	271		T5	353
valid_sources[0x61]	616258	1			T1	461		T2	293		T5	407
valid_sources[0x62]	593045	1			T1	526		T2	303		T4	5640
valid_sources[0x63]	611531	1			T1	498		T2	357		T5	394
valid_sources[0x64]	611452	1			T1	532		T2	418		T5	338
valid_sources[0x65]	602539	1			T1	481		T2	337		T5	363
valid_sources[0x66]	581274	1			T1	497		T2	325		T5	410
valid_sources[0x67]	931525	1			T1	515		T2	299		T5	445
valid_sources[0x68]	598563	1			T1	469		T2	312		T5	358
valid_sources[0x69]	584106	1			T1	487		T2	372		T5	380
valid_sources[0x6a]	2034258	1			T1	521		T2	364		T4	6597
valid_sources[0x6b]	573344	1			T1	508		T2	426		T5	359
valid_sources[0x6c]	588638	1			T1	508		T2	290		T5	395
valid_sources[0x6d]	657796	1			T1	502		T2	326		T5	403
valid_sources[0x6e]	593871	1			T1	509		T2	363		T5	383
valid_sources[0x6f]	745754	1			T1	494		T2	276		T5	354
valid_sources[0x70]	626735	1			T1	505		T2	444		T5	400
valid_sources[0x71]	560831	1			T1	481		T2	273		T5	387
valid_sources[0x72]	584145	1			T1	463		T2	241		T5	399
valid_sources[0x73]	776609	1			T1	555		T2	237		T5	387
valid_sources[0x74]	576059	1			T1	473		T2	365		T5	327
valid_sources[0x75]	574161	1			T1	448		T2	272		T5	295
valid_sources[0x76]	617348	1			T1	515		T2	296		T5	330
valid_sources[0x77]	604836	1			T1	522		T2	255		T4	2967
valid_sources[0x78]	587625	1			T1	507		T2	390		T5	393
valid_sources[0x79]	686458	1			T1	565		T2	196		T5	406
valid_sources[0x7a]	1805751	1			T1	465		T2	278		T5	329
valid_sources[0x7b]	1546905	1			T1	462		T2	329		T5	353
valid_sources[0x7c]	584086	1			T1	493		T2	218		T5	426
valid_sources[0x7d]	570894	1			T1	531		T2	259		T5	374
valid_sources[0x7e]	581541	1			T1	447		T2	338		T5	323
valid_sources[0x7f]	611872	1			T1	464		T2	366		T5	424
valid_sources[0x80]	573408	1			T1	490		T2	319		T5	373

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

82378326

1

T1

57927

T2

37251

T4

64184

values[0x0]

all_enables

biggest_size

42534249

1

T1

28781

T2

18711

T4

32089

values[0x1]

all_enables

biggest_size

42533546

1

T1

28764

T2

18635

T4

32148

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	34825	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162637

1

T1

4

T2

5

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56825	1			T6	28		T18	6		T32	389
values[0x0]	67811	1			T1	5		T2	7		T3	4
values[0x1]	72826	1			T1	10		T2	10		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26160	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

171302

1

T1

4

T2

7

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1049	1			T32	2		T34	20		T50	14
valid_sources[0x01]	506	1			T32	3		T33	8		T34	24
valid_sources[0x02]	758	1			T32	4		T34	26		T52	1
valid_sources[0x03]	878	1			T32	6		T33	139		T34	20
valid_sources[0x04]	543	1			T32	7		T33	3		T34	25
valid_sources[0x05]	737	1			T19	2		T32	4		T34	25
valid_sources[0x06]	787	1			T19	2		T32	7		T33	126
valid_sources[0x07]	569	1			T32	4		T34	26		T137	1
valid_sources[0x08]	614	1			T32	1		T34	33		T50	15
valid_sources[0x09]	692	1			T1	1		T3	2		T32	8
valid_sources[0x0a]	757	1			T32	1		T33	2		T34	27
valid_sources[0x0b]	667	1			T32	3		T33	1		T34	29
valid_sources[0x0c]	777	1			T32	6		T34	17		T50	10
valid_sources[0x0d]	532	1			T32	3		T34	14		T52	1
valid_sources[0x0e]	986	1			T32	9		T33	1		T34	22
valid_sources[0x0f]	620	1			T32	6		T34	22		T50	16
valid_sources[0x10]	1095	1			T100	1		T32	6		T34	27
valid_sources[0x11]	801	1			T18	1		T32	10		T34	29
valid_sources[0x12]	776	1			T18	2		T19	2		T32	6
valid_sources[0x13]	567	1			T32	3		T33	4		T34	16
valid_sources[0x14]	502	1			T32	6		T34	24		T50	9
valid_sources[0x15]	566	1			T28	20		T32	3		T34	30
valid_sources[0x16]	636	1			T32	5		T57	1		T34	30
valid_sources[0x17]	894	1			T32	3		T34	18		T52	1
valid_sources[0x18]	829	1			T32	3		T33	116		T34	36
valid_sources[0x19]	937	1			T32	5		T34	11		T59	1
valid_sources[0x1a]	814	1			T32	1		T34	29		T153	1
valid_sources[0x1b]	1137	1			T19	2		T32	8		T33	201
valid_sources[0x1c]	848	1			T32	3		T34	21		T50	9
valid_sources[0x1d]	729	1			T32	5		T34	37		T52	2
valid_sources[0x1e]	786	1			T32	7		T34	26		T154	2
valid_sources[0x1f]	592	1			T32	3		T33	1		T34	27
valid_sources[0x20]	952	1			T32	5		T33	149		T34	17
valid_sources[0x21]	576	1			T32	8		T33	3		T34	20
valid_sources[0x22]	837	1			T32	9		T33	72		T34	17
valid_sources[0x23]	601	1			T32	5		T34	18		T52	2
valid_sources[0x24]	715	1			T32	7		T33	71		T34	23
valid_sources[0x25]	847	1			T1	1		T32	11		T34	25
valid_sources[0x26]	757	1			T3	1		T32	6		T33	2
valid_sources[0x27]	767	1			T3	1		T32	4		T33	1
valid_sources[0x28]	1027	1			T32	8		T34	13		T24	1
valid_sources[0x29]	1097	1			T32	5		T33	3		T34	20
valid_sources[0x2a]	529	1			T32	4		T34	18		T29	3
valid_sources[0x2b]	566	1			T32	3		T33	1		T34	19
valid_sources[0x2c]	695	1			T32	5		T33	1		T34	26
valid_sources[0x2d]	517	1			T18	1		T20	15		T100	1
valid_sources[0x2e]	759	1			T32	5		T33	3		T34	22
valid_sources[0x2f]	590	1			T32	3		T34	24		T50	16
valid_sources[0x30]	796	1			T32	7		T34	21		T8	2
valid_sources[0x31]	499	1			T32	8		T33	2		T34	20
valid_sources[0x32]	838	1			T18	1		T32	6		T34	16
valid_sources[0x33]	786	1			T32	8		T33	1		T34	20
valid_sources[0x34]	732	1			T32	3		T34	12		T50	7
valid_sources[0x35]	514	1			T18	1		T32	9		T33	1
valid_sources[0x36]	652	1			T32	4		T34	30		T29	1
valid_sources[0x37]	705	1			T32	3		T34	29		T29	5
valid_sources[0x38]	515	1			T32	5		T34	21		T107	3
valid_sources[0x39]	688	1			T32	9		T34	22		T155	2
valid_sources[0x3a]	484	1			T18	2		T32	5		T34	16
valid_sources[0x3b]	595	1			T32	9		T33	1		T34	14
valid_sources[0x3c]	1338	1			T32	6		T33	75		T34	40
valid_sources[0x3d]	815	1			T100	1		T32	5		T33	1
valid_sources[0x3e]	599	1			T32	4		T33	3		T34	20
valid_sources[0x3f]	489	1			T32	7		T34	32		T29	2
valid_sources[0x40]	1263	1			T32	5		T33	1		T34	32
valid_sources[0x41]	877	1			T32	3		T33	3		T34	21
valid_sources[0x42]	795	1			T14	1		T32	7		T33	3
valid_sources[0x43]	755	1			T32	6		T33	3		T34	26
valid_sources[0x44]	661	1			T32	8		T34	13		T52	63
valid_sources[0x45]	762	1			T18	1		T100	1		T32	4
valid_sources[0x46]	529	1			T101	2		T32	5		T34	20
valid_sources[0x47]	1114	1			T1	1		T32	3		T33	188
valid_sources[0x48]	937	1			T32	8		T33	141		T34	14
valid_sources[0x49]	728	1			T18	2		T32	7		T33	183
valid_sources[0x4a]	722	1			T17	2		T32	9		T34	30
valid_sources[0x4b]	810	1			T3	1		T32	2		T34	21
valid_sources[0x4c]	654	1			T32	1		T34	27		T137	1
valid_sources[0x4d]	839	1			T32	5		T33	2		T34	26
valid_sources[0x4e]	720	1			T32	6		T33	4		T34	13
valid_sources[0x4f]	611	1			T32	8		T33	1		T34	24
valid_sources[0x50]	754	1			T32	3		T34	7		T60	1
valid_sources[0x51]	661	1			T32	7		T33	1		T34	22
valid_sources[0x52]	708	1			T32	6		T33	151		T34	27
valid_sources[0x53]	654	1			T32	5		T33	3		T34	20
valid_sources[0x54]	829	1			T32	7		T7	54		T34	26
valid_sources[0x55]	533	1			T32	9		T34	26		T50	17
valid_sources[0x56]	866	1			T32	9		T33	5		T34	24
valid_sources[0x57]	554	1			T32	5		T33	1		T34	21
valid_sources[0x58]	631	1			T32	3		T33	79		T34	21
valid_sources[0x59]	925	1			T32	2		T33	79		T34	19
valid_sources[0x5a]	916	1			T32	6		T34	22		T8	20
valid_sources[0x5b]	747	1			T32	9		T34	18		T23	3
valid_sources[0x5c]	979	1			T100	1		T32	2		T33	3
valid_sources[0x5d]	692	1			T19	1		T32	6		T33	1
valid_sources[0x5e]	621	1			T3	3		T32	3		T33	23
valid_sources[0x5f]	704	1			T32	1		T34	28		T137	1
valid_sources[0x60]	1168	1			T4	11		T32	3		T33	54
valid_sources[0x61]	853	1			T14	1		T102	1		T32	7
valid_sources[0x62]	835	1			T32	4		T33	117		T34	18
valid_sources[0x63]	994	1			T32	8		T34	19		T50	7
valid_sources[0x64]	861	1			T32	6		T34	21		T154	2
valid_sources[0x65]	587	1			T32	7		T34	18		T8	1
valid_sources[0x66]	593	1			T32	4		T34	33		T50	5
valid_sources[0x67]	649	1			T32	7		T34	35		T50	13
valid_sources[0x68]	618	1			T32	3		T34	27		T52	11
valid_sources[0x69]	831	1			T32	5		T33	121		T34	18
valid_sources[0x6a]	553	1			T20	12		T32	3		T33	2
valid_sources[0x6b]	893	1			T32	6		T34	10		T23	1
valid_sources[0x6c]	776	1			T18	1		T32	2		T34	29
valid_sources[0x6d]	497	1			T32	1		T34	24		T49	1
valid_sources[0x6e]	730	1			T32	5		T34	15		T49	1
valid_sources[0x6f]	627	1			T65	2		T100	1		T32	4
valid_sources[0x70]	944	1			T32	11		T33	1		T34	14
valid_sources[0x71]	699	1			T32	7		T34	21		T52	1
valid_sources[0x72]	1007	1			T19	3		T32	6		T34	14
valid_sources[0x73]	1003	1			T32	8		T33	179		T34	20
valid_sources[0x74]	463	1			T32	5		T33	1		T34	21
valid_sources[0x75]	866	1			T32	4		T33	111		T34	16
valid_sources[0x76]	920	1			T1	2		T19	3		T32	7
valid_sources[0x77]	949	1			T32	5		T33	97		T34	22
valid_sources[0x78]	1256	1			T32	9		T33	2		T34	27
valid_sources[0x79]	774	1			T18	3		T32	6		T34	14
valid_sources[0x7a]	859	1			T32	13		T34	18		T50	11
valid_sources[0x7b]	730	1			T32	8		T34	29		T49	2
valid_sources[0x7c]	790	1			T32	2		T33	111		T34	24
valid_sources[0x7d]	798	1			T32	5		T34	21		T29	4
valid_sources[0x7e]	646	1			T32	3		T33	1		T34	14
valid_sources[0x7f]	732	1			T12	2		T18	1		T20	1
valid_sources[0x80]	865	1			T32	10		T33	1		T34	26

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

44245

1

T6

21

T18

3

T32

327

values[0x0]

all_enables

biggest_size

59983

1

T1

1

T2

3

T3

1

values[0x1]

all_enables

biggest_size

58409

1

T1

3

T2

2

T6

6