Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

16688491

1

T1

11692

T2

7452

T4

12867

full_word

164231594

1

T1

115472

T2

74597

T4

128421

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	180919795	1			T1	127164		T2	82049		T4	141288
auto[TlIntgErrCmd]	89	1			T114	4		T115	7		T116	2
auto[TlIntgErrData]	111	1			T114	6		T115	7		T116	4
auto[TlIntgErrBoth]	90	1			T115	6		T116	4		T125	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

87382460

1

T1

63816

T2

40984

T4

70583

auto[1]

93537625

1

T1

63348

T2

41065

T4

70705

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	8164176	1			T1	5889		T2	3733		T4	6399
auto[TlIntgErrNone]	partial	auto[1]	8524045	1			T1	5803		T2	3719		T4	6468
auto[TlIntgErrNone]	full_word	auto[0]	79218142	1			T1	57927		T2	37251		T4	64184
auto[TlIntgErrNone]	full_word	auto[1]	85013432	1			T1	57545		T2	37346		T4	64237
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T114	2		T115	3		T116	1
auto[TlIntgErrCmd]	partial	auto[1]	44	1			T114	2		T115	3		T125	4
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T115	1		T116	1		T136	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1			T125	2		T131	1		T129	1
auto[TlIntgErrData]	partial	auto[0]	63	1			T114	2		T115	6		T116	3
auto[TlIntgErrData]	partial	auto[1]	45	1			T114	3		T115	1		T116	1
auto[TlIntgErrData]	full_word	auto[0]	2	1			T114	1		T135	1		-	-
auto[TlIntgErrData]	full_word	auto[1]	1	1			T133	1		-	-		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1			T115	2		T125	3		T131	2
auto[TlIntgErrBoth]	partial	auto[1]	48	1			T115	4		T116	3		T125	2
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T125	1		T126	1		T130	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T116	1		T126	1		T129	1