Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	800506	1			T14	16299		T15	7390		T16	748
auto[1]	10814262	1			T1	37295		T2	25270		T4	1785
auto[2]	616128	1			T14	14767		T15	4665		T16	734
auto[3]	10515588	1			T1	36890		T2	25195		T4	1764

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14145263	1			T1	61117		T2	42128		T4	2480
auto[1]	2111702	1			T1	6264		T2	3965		T4	498
auto[2]	2139941	1			T1	6176		T2	3961		T4	495
auto[3]	4349578	1			T1	628		T2	411		T4	76

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9842667

1

T1

74184

T2

50465

T4

3548

auto[1]

12903817

1

T1

1

T4

1

T14

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	420253	1			T14	13437		T15	6115		T16	22
auto[0]	auto[0]	auto[1]	43615	1			T14	1369		T15	603		T16	104
auto[0]	auto[0]	auto[2]	43272	1			T14	1367		T15	608		T16	99
auto[0]	auto[0]	auto[3]	93376	1			T14	126		T15	64		T16	523
auto[0]	auto[1]	auto[0]	3272293	1			T1	30669		T2	21084		T4	1240
auto[0]	auto[1]	auto[1]	357797	1			T1	3197		T2	1893		T4	384
auto[0]	auto[1]	auto[2]	368919	1			T1	3111		T2	2096		T4	118
auto[0]	auto[1]	auto[3]	526735	1			T1	318		T2	197		T4	42
auto[0]	auto[2]	auto[0]	315043	1			T14	12276		T15	3586		T16	24
auto[0]	auto[2]	auto[1]	38629	1			T14	1228		T15	354		T16	115
auto[0]	auto[2]	auto[2]	30089	1			T14	1149		T15	679		T16	103
auto[0]	auto[2]	auto[3]	67301	1			T14	113		T15	46		T16	492
auto[0]	auto[3]	auto[0]	3074307	1			T1	30447		T2	21044		T4	1239
auto[0]	auto[3]	auto[1]	344906	1			T1	3067		T2	2072		T4	114
auto[0]	auto[3]	auto[2]	371005	1			T1	3065		T2	1865		T4	377
auto[0]	auto[3]	auto[3]	475127	1			T1	310		T2	214		T4	34
auto[1]	auto[0]	auto[0]	6579	1			T49	1		T112	548		T146	1
auto[1]	auto[0]	auto[1]	29576	1			T112	2412		T147	2250		T148	2827
auto[1]	auto[0]	auto[2]	29779	1			T112	2462		T149	1		T147	2252
auto[1]	auto[0]	auto[3]	134056	1			T112	10791		T144	2		T145	2
auto[1]	auto[1]	auto[0]	3526913	1			T4	1		T48	2794		T22	1
auto[1]	auto[1]	auto[1]	648155	1			T48	11549		T107	6103		T108	9514
auto[1]	auto[1]	auto[2]	630504	1			T48	12725		T22	1		T107	6662
auto[1]	auto[1]	auto[3]	1482946	1			T48	50907		T107	580		T108	999
auto[1]	auto[2]	auto[0]	5501	1			T14	1		T112	333		T150	1
auto[1]	auto[2]	auto[1]	24517	1			T112	1408		T147	1332		T148	2603
auto[1]	auto[2]	auto[2]	24511	1			T112	2627		T147	2532		T148	1927
auto[1]	auto[2]	auto[3]	110537	1			T112	11881		T151	1		T147	11335
auto[1]	auto[3]	auto[0]	3524374	1			T1	1		T48	2848		T107	67312
auto[1]	auto[3]	auto[1]	624507	1			T48	12504		T107	6866		T108	10570
auto[1]	auto[3]	auto[2]	641862	1			T48	11261		T107	6209		T108	9561
auto[1]	auto[3]	auto[3]	1459500	1			T48	51247		T107	599		T108	947