Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1164220702	156526	0	0
ctrl_regwen_rd_A	1164220702	7585	0	0
exec_rd_A	1164220702	6948	0	0
exec_regwen_rd_A	1164220702	7320	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164220702	156526	0	0
T7	822653	0	0	0
T8	117317	0	0	0
T22	126945	0	0	0
T32	51333	1607	0	0
T33	157538	4630	0	0
T34	245858	5955	0	0
T50	0	3528	0	0
T51	0	4521	0	0
T52	0	1613	0	0
T53	0	2523	0	0
T54	0	833	0	0
T55	0	6044	0	0
T56	0	2593	0	0
T57	70598	0	0	0
T58	74542	0	0	0
T59	118888	0	0	0
T60	103574	0	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164220702	7585	0	0
T7	822653	0	0	0
T8	117317	0	0	0
T22	126945	0	0	0
T32	51333	113	0	0
T33	157538	0	0	0
T34	245858	0	0	0
T51	0	1034	0	0
T52	0	337	0	0
T56	0	706	0	0
T57	70598	0	0	0
T58	74542	0	0	0
T59	118888	0	0	0
T60	103574	0	0	0
T117	0	447	0	0
T118	0	140	0	0
T119	0	49	0	0
T120	0	364	0	0
T121	0	198	0	0
T122	0	438	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164220702	6948	0	0
T7	822653	0	0	0
T8	117317	0	0	0
T22	126945	0	0	0
T32	51333	139	0	0
T33	157538	0	0	0
T34	245858	0	0	0
T51	0	788	0	0
T52	0	277	0	0
T56	0	664	0	0
T57	70598	0	0	0
T58	74542	0	0	0
T59	118888	0	0	0
T60	103574	0	0	0
T117	0	466	0	0
T118	0	193	0	0
T119	0	47	0	0
T120	0	292	0	0
T121	0	174	0	0
T122	0	351	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1164220702	7320	0	0
T7	822653	0	0	0
T8	117317	0	0	0
T22	126945	0	0	0
T32	51333	154	0	0
T33	157538	0	0	0
T34	245858	0	0	0
T51	0	722	0	0
T52	0	264	0	0
T56	0	784	0	0
T57	70598	0	0	0
T58	74542	0	0	0
T59	118888	0	0	0
T60	103574	0	0	0
T117	0	457	0	0
T118	0	173	0	0
T119	0	32	0	0
T120	0	391	0	0
T121	0	220	0	0
T122	0	416	0	0