| T795 |
/workspace/coverage/default/46.sram_ctrl_mem_partial_access.1538882747 |
|
|
Apr 04 01:59:51 PM PDT 24 |
Apr 04 02:01:05 PM PDT 24 |
2468131097 ps |
| T796 |
/workspace/coverage/default/39.sram_ctrl_bijection.4228475251 |
|
|
Apr 04 01:57:03 PM PDT 24 |
Apr 04 02:27:40 PM PDT 24 |
105943649009 ps |
| T797 |
/workspace/coverage/default/34.sram_ctrl_max_throughput.3432176904 |
|
|
Apr 04 01:54:23 PM PDT 24 |
Apr 04 01:55:05 PM PDT 24 |
3356877360 ps |
| T798 |
/workspace/coverage/default/23.sram_ctrl_smoke.3619297142 |
|
|
Apr 04 01:45:33 PM PDT 24 |
Apr 04 01:46:57 PM PDT 24 |
4167524207 ps |
| T799 |
/workspace/coverage/default/24.sram_ctrl_regwen.1062324391 |
|
|
Apr 04 01:46:32 PM PDT 24 |
Apr 04 01:53:56 PM PDT 24 |
4650108018 ps |
| T800 |
/workspace/coverage/default/27.sram_ctrl_stress_all.2231769916 |
|
|
Apr 04 01:49:35 PM PDT 24 |
Apr 04 02:40:50 PM PDT 24 |
408947881163 ps |
| T801 |
/workspace/coverage/default/17.sram_ctrl_ram_cfg.574403670 |
|
|
Apr 04 01:41:50 PM PDT 24 |
Apr 04 01:41:54 PM PDT 24 |
365933982 ps |
| T802 |
/workspace/coverage/default/35.sram_ctrl_bijection.3551782935 |
|
|
Apr 04 01:54:37 PM PDT 24 |
Apr 04 02:38:10 PM PDT 24 |
119825833367 ps |
| T803 |
/workspace/coverage/default/49.sram_ctrl_multiple_keys.2037296166 |
|
|
Apr 04 02:00:48 PM PDT 24 |
Apr 04 02:09:13 PM PDT 24 |
16041012790 ps |
| T804 |
/workspace/coverage/default/18.sram_ctrl_ram_cfg.2209803258 |
|
|
Apr 04 01:42:24 PM PDT 24 |
Apr 04 01:42:27 PM PDT 24 |
361125010 ps |
| T805 |
/workspace/coverage/default/17.sram_ctrl_alert_test.3610562605 |
|
|
Apr 04 01:41:50 PM PDT 24 |
Apr 04 01:41:51 PM PDT 24 |
54702977 ps |
| T806 |
/workspace/coverage/default/43.sram_ctrl_throughput_w_partial_write.536327928 |
|
|
Apr 04 01:58:47 PM PDT 24 |
Apr 04 01:58:55 PM PDT 24 |
5211553331 ps |
| T807 |
/workspace/coverage/default/45.sram_ctrl_regwen.2324979702 |
|
|
Apr 04 01:59:28 PM PDT 24 |
Apr 04 02:10:21 PM PDT 24 |
12199500437 ps |
| T808 |
/workspace/coverage/default/49.sram_ctrl_stress_all.1851686309 |
|
|
Apr 04 02:00:56 PM PDT 24 |
Apr 04 03:18:57 PM PDT 24 |
152918322917 ps |
| T809 |
/workspace/coverage/default/38.sram_ctrl_multiple_keys.3970661336 |
|
|
Apr 04 01:56:41 PM PDT 24 |
Apr 04 02:20:06 PM PDT 24 |
30018480877 ps |
| T810 |
/workspace/coverage/default/25.sram_ctrl_smoke.2574514631 |
|
|
Apr 04 01:46:47 PM PDT 24 |
Apr 04 01:47:29 PM PDT 24 |
855306454 ps |
| T811 |
/workspace/coverage/default/34.sram_ctrl_mem_walk.3014836393 |
|
|
Apr 04 01:54:27 PM PDT 24 |
Apr 04 01:59:46 PM PDT 24 |
158797903702 ps |
| T812 |
/workspace/coverage/default/30.sram_ctrl_stress_pipeline.375972909 |
|
|
Apr 04 01:51:29 PM PDT 24 |
Apr 04 01:54:39 PM PDT 24 |
21621746036 ps |
| T813 |
/workspace/coverage/default/14.sram_ctrl_smoke.680488684 |
|
|
Apr 04 01:39:31 PM PDT 24 |
Apr 04 01:42:06 PM PDT 24 |
2548983268 ps |
| T814 |
/workspace/coverage/default/2.sram_ctrl_access_during_key_req.985661421 |
|
|
Apr 04 01:35:26 PM PDT 24 |
Apr 04 02:02:53 PM PDT 24 |
95090329867 ps |
| T815 |
/workspace/coverage/default/36.sram_ctrl_max_throughput.55675181 |
|
|
Apr 04 01:55:24 PM PDT 24 |
Apr 04 01:55:58 PM PDT 24 |
1642190194 ps |
| T816 |
/workspace/coverage/default/13.sram_ctrl_multiple_keys.1619334861 |
|
|
Apr 04 01:39:03 PM PDT 24 |
Apr 04 01:52:09 PM PDT 24 |
13785454222 ps |
| T817 |
/workspace/coverage/default/28.sram_ctrl_partial_access_b2b.1635466945 |
|
|
Apr 04 01:50:12 PM PDT 24 |
Apr 04 01:54:27 PM PDT 24 |
5061396780 ps |
| T818 |
/workspace/coverage/default/40.sram_ctrl_lc_escalation.980339417 |
|
|
Apr 04 01:57:45 PM PDT 24 |
Apr 04 01:57:51 PM PDT 24 |
720261085 ps |
| T819 |
/workspace/coverage/default/15.sram_ctrl_alert_test.1481453782 |
|
|
Apr 04 01:40:54 PM PDT 24 |
Apr 04 01:40:55 PM PDT 24 |
15783963 ps |
| T820 |
/workspace/coverage/default/36.sram_ctrl_alert_test.3693385644 |
|
|
Apr 04 01:56:01 PM PDT 24 |
Apr 04 01:56:02 PM PDT 24 |
35001964 ps |
| T821 |
/workspace/coverage/default/10.sram_ctrl_executable.2911486885 |
|
|
Apr 04 01:37:43 PM PDT 24 |
Apr 04 01:40:38 PM PDT 24 |
5463266062 ps |
| T822 |
/workspace/coverage/default/0.sram_ctrl_ram_cfg.2546459778 |
|
|
Apr 04 01:35:17 PM PDT 24 |
Apr 04 01:35:20 PM PDT 24 |
694142900 ps |
| T823 |
/workspace/coverage/default/32.sram_ctrl_multiple_keys.3977652241 |
|
|
Apr 04 01:53:02 PM PDT 24 |
Apr 04 01:59:56 PM PDT 24 |
8330778694 ps |
| T824 |
/workspace/coverage/default/41.sram_ctrl_smoke.1788659046 |
|
|
Apr 04 01:57:46 PM PDT 24 |
Apr 04 01:58:06 PM PDT 24 |
1117004477 ps |
| T825 |
/workspace/coverage/default/47.sram_ctrl_bijection.1018652407 |
|
|
Apr 04 01:59:50 PM PDT 24 |
Apr 04 02:39:54 PM PDT 24 |
230116534709 ps |
| T826 |
/workspace/coverage/default/21.sram_ctrl_stress_all.3033243902 |
|
|
Apr 04 01:44:41 PM PDT 24 |
Apr 04 02:48:44 PM PDT 24 |
65744740636 ps |
| T827 |
/workspace/coverage/default/23.sram_ctrl_bijection.2076818675 |
|
|
Apr 04 01:45:34 PM PDT 24 |
Apr 04 02:00:34 PM PDT 24 |
42904413979 ps |
| T828 |
/workspace/coverage/default/20.sram_ctrl_stress_pipeline.4070013296 |
|
|
Apr 04 01:43:19 PM PDT 24 |
Apr 04 01:45:45 PM PDT 24 |
4289771007 ps |
| T829 |
/workspace/coverage/default/28.sram_ctrl_ram_cfg.2261276942 |
|
|
Apr 04 01:50:23 PM PDT 24 |
Apr 04 01:50:26 PM PDT 24 |
696719606 ps |
| T830 |
/workspace/coverage/default/8.sram_ctrl_lc_escalation.410333465 |
|
|
Apr 04 01:36:43 PM PDT 24 |
Apr 04 01:37:54 PM PDT 24 |
12562343513 ps |
| T831 |
/workspace/coverage/default/12.sram_ctrl_stress_all.2137002284 |
|
|
Apr 04 01:38:52 PM PDT 24 |
Apr 04 02:44:02 PM PDT 24 |
778312399148 ps |
| T832 |
/workspace/coverage/default/24.sram_ctrl_ram_cfg.3375421003 |
|
|
Apr 04 01:46:32 PM PDT 24 |
Apr 04 01:46:35 PM PDT 24 |
704037147 ps |
| T833 |
/workspace/coverage/default/27.sram_ctrl_regwen.725258935 |
|
|
Apr 04 01:49:24 PM PDT 24 |
Apr 04 02:08:48 PM PDT 24 |
36609202134 ps |
| T834 |
/workspace/coverage/default/44.sram_ctrl_mem_walk.1436537422 |
|
|
Apr 04 01:59:08 PM PDT 24 |
Apr 04 02:03:04 PM PDT 24 |
3946316863 ps |
| T835 |
/workspace/coverage/default/43.sram_ctrl_multiple_keys.3729331783 |
|
|
Apr 04 01:58:44 PM PDT 24 |
Apr 04 02:18:18 PM PDT 24 |
10656914382 ps |
| T836 |
/workspace/coverage/default/36.sram_ctrl_ram_cfg.1388060394 |
|
|
Apr 04 01:55:49 PM PDT 24 |
Apr 04 01:55:53 PM PDT 24 |
359739743 ps |
| T837 |
/workspace/coverage/default/11.sram_ctrl_max_throughput.942972769 |
|
|
Apr 04 01:38:14 PM PDT 24 |
Apr 04 01:39:26 PM PDT 24 |
789978842 ps |
| T838 |
/workspace/coverage/default/42.sram_ctrl_regwen.3717969909 |
|
|
Apr 04 01:58:34 PM PDT 24 |
Apr 04 02:08:46 PM PDT 24 |
4664607088 ps |
| T839 |
/workspace/coverage/default/23.sram_ctrl_max_throughput.931495727 |
|
|
Apr 04 01:45:46 PM PDT 24 |
Apr 04 01:45:52 PM PDT 24 |
1331006513 ps |
| T840 |
/workspace/coverage/default/24.sram_ctrl_mem_walk.3973966067 |
|
|
Apr 04 01:46:37 PM PDT 24 |
Apr 04 01:49:07 PM PDT 24 |
28710270160 ps |
| T841 |
/workspace/coverage/default/37.sram_ctrl_executable.3307103285 |
|
|
Apr 04 01:56:41 PM PDT 24 |
Apr 04 02:16:47 PM PDT 24 |
11003136836 ps |
| T842 |
/workspace/coverage/default/26.sram_ctrl_smoke.2405507974 |
|
|
Apr 04 01:47:28 PM PDT 24 |
Apr 04 01:48:27 PM PDT 24 |
898435078 ps |
| T843 |
/workspace/coverage/default/8.sram_ctrl_smoke.989550025 |
|
|
Apr 04 01:36:45 PM PDT 24 |
Apr 04 01:37:08 PM PDT 24 |
3432926250 ps |
| T844 |
/workspace/coverage/default/14.sram_ctrl_max_throughput.3383014591 |
|
|
Apr 04 01:39:52 PM PDT 24 |
Apr 04 01:42:32 PM PDT 24 |
2385126382 ps |
| T845 |
/workspace/coverage/default/26.sram_ctrl_alert_test.3507307443 |
|
|
Apr 04 01:48:31 PM PDT 24 |
Apr 04 01:48:31 PM PDT 24 |
39361842 ps |
| T846 |
/workspace/coverage/default/35.sram_ctrl_executable.3199760646 |
|
|
Apr 04 01:54:55 PM PDT 24 |
Apr 04 02:14:02 PM PDT 24 |
44722545107 ps |
| T847 |
/workspace/coverage/default/45.sram_ctrl_partial_access_b2b.274286474 |
|
|
Apr 04 01:59:18 PM PDT 24 |
Apr 04 02:05:53 PM PDT 24 |
78742082090 ps |
| T848 |
/workspace/coverage/default/36.sram_ctrl_stress_pipeline.4240229577 |
|
|
Apr 04 01:55:16 PM PDT 24 |
Apr 04 01:58:38 PM PDT 24 |
12056280338 ps |
| T849 |
/workspace/coverage/default/8.sram_ctrl_access_during_key_req.1177902305 |
|
|
Apr 04 01:36:42 PM PDT 24 |
Apr 04 01:57:57 PM PDT 24 |
57552030930 ps |
| T850 |
/workspace/coverage/default/44.sram_ctrl_max_throughput.4203535248 |
|
|
Apr 04 01:59:00 PM PDT 24 |
Apr 04 01:59:34 PM PDT 24 |
2815645271 ps |
| T851 |
/workspace/coverage/default/30.sram_ctrl_regwen.1570151216 |
|
|
Apr 04 01:51:58 PM PDT 24 |
Apr 04 02:05:10 PM PDT 24 |
8764021788 ps |
| T852 |
/workspace/coverage/default/35.sram_ctrl_lc_escalation.129976964 |
|
|
Apr 04 01:54:55 PM PDT 24 |
Apr 04 01:56:05 PM PDT 24 |
21502783908 ps |
| T853 |
/workspace/coverage/default/3.sram_ctrl_stress_all.2471950747 |
|
|
Apr 04 01:35:44 PM PDT 24 |
Apr 04 01:56:41 PM PDT 24 |
13008749554 ps |
| T854 |
/workspace/coverage/default/25.sram_ctrl_stress_all_with_rand_reset.1392979970 |
|
|
Apr 04 01:47:29 PM PDT 24 |
Apr 04 01:50:06 PM PDT 24 |
12356952127 ps |
| T855 |
/workspace/coverage/default/49.sram_ctrl_bijection.712041131 |
|
|
Apr 04 02:00:44 PM PDT 24 |
Apr 04 02:24:23 PM PDT 24 |
21318372474 ps |
| T856 |
/workspace/coverage/default/20.sram_ctrl_throughput_w_partial_write.2789306153 |
|
|
Apr 04 01:43:28 PM PDT 24 |
Apr 04 01:44:16 PM PDT 24 |
772470670 ps |
| T857 |
/workspace/coverage/default/25.sram_ctrl_stress_pipeline.655298281 |
|
|
Apr 04 01:47:02 PM PDT 24 |
Apr 04 01:51:12 PM PDT 24 |
4717993978 ps |
| T858 |
/workspace/coverage/default/24.sram_ctrl_multiple_keys.1700269628 |
|
|
Apr 04 01:46:03 PM PDT 24 |
Apr 04 02:06:28 PM PDT 24 |
129727761905 ps |
| T859 |
/workspace/coverage/default/41.sram_ctrl_partial_access.10141044 |
|
|
Apr 04 01:57:58 PM PDT 24 |
Apr 04 01:59:22 PM PDT 24 |
15683347198 ps |
| T860 |
/workspace/coverage/default/39.sram_ctrl_stress_pipeline.256371083 |
|
|
Apr 04 01:56:56 PM PDT 24 |
Apr 04 02:01:21 PM PDT 24 |
4768054985 ps |
| T861 |
/workspace/coverage/default/13.sram_ctrl_ram_cfg.1493346247 |
|
|
Apr 04 01:39:13 PM PDT 24 |
Apr 04 01:39:16 PM PDT 24 |
347069345 ps |
| T862 |
/workspace/coverage/default/22.sram_ctrl_lc_escalation.2085381110 |
|
|
Apr 04 01:45:05 PM PDT 24 |
Apr 04 01:45:28 PM PDT 24 |
14400926243 ps |
| T863 |
/workspace/coverage/default/32.sram_ctrl_stress_pipeline.2424143195 |
|
|
Apr 04 01:53:01 PM PDT 24 |
Apr 04 01:57:12 PM PDT 24 |
5029547560 ps |
| T864 |
/workspace/coverage/default/36.sram_ctrl_multiple_keys.2363533233 |
|
|
Apr 04 01:55:16 PM PDT 24 |
Apr 04 02:05:11 PM PDT 24 |
80599897002 ps |
| T865 |
/workspace/coverage/default/17.sram_ctrl_access_during_key_req.1611538352 |
|
|
Apr 04 01:41:41 PM PDT 24 |
Apr 04 01:52:28 PM PDT 24 |
92917241667 ps |
| T866 |
/workspace/coverage/default/34.sram_ctrl_multiple_keys.4027230965 |
|
|
Apr 04 01:53:54 PM PDT 24 |
Apr 04 01:55:14 PM PDT 24 |
2608599736 ps |
| T867 |
/workspace/coverage/default/44.sram_ctrl_throughput_w_partial_write.1962095398 |
|
|
Apr 04 01:59:09 PM PDT 24 |
Apr 04 01:59:50 PM PDT 24 |
5275778439 ps |
| T868 |
/workspace/coverage/default/11.sram_ctrl_executable.3250030113 |
|
|
Apr 04 01:38:12 PM PDT 24 |
Apr 04 01:49:51 PM PDT 24 |
21939193915 ps |
| T869 |
/workspace/coverage/default/40.sram_ctrl_access_during_key_req.2491100400 |
|
|
Apr 04 01:57:38 PM PDT 24 |
Apr 04 02:06:10 PM PDT 24 |
20853784600 ps |
| T870 |
/workspace/coverage/default/22.sram_ctrl_regwen.2665109589 |
|
|
Apr 04 01:45:16 PM PDT 24 |
Apr 04 02:01:06 PM PDT 24 |
18838805497 ps |
| T871 |
/workspace/coverage/default/5.sram_ctrl_smoke.2877090342 |
|
|
Apr 04 01:35:54 PM PDT 24 |
Apr 04 01:36:00 PM PDT 24 |
4547990651 ps |
| T872 |
/workspace/coverage/default/28.sram_ctrl_max_throughput.2289972210 |
|
|
Apr 04 01:50:14 PM PDT 24 |
Apr 04 01:50:28 PM PDT 24 |
769429603 ps |
| T873 |
/workspace/coverage/default/43.sram_ctrl_stress_pipeline.3488337656 |
|
|
Apr 04 01:58:45 PM PDT 24 |
Apr 04 02:03:14 PM PDT 24 |
8831288599 ps |
| T874 |
/workspace/coverage/default/37.sram_ctrl_partial_access.3312714466 |
|
|
Apr 04 01:56:19 PM PDT 24 |
Apr 04 01:56:30 PM PDT 24 |
2814835112 ps |
| T875 |
/workspace/coverage/default/36.sram_ctrl_access_during_key_req.1763963844 |
|
|
Apr 04 01:55:40 PM PDT 24 |
Apr 04 01:56:12 PM PDT 24 |
1607062716 ps |
| T876 |
/workspace/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1143345057 |
|
|
Apr 04 01:35:46 PM PDT 24 |
Apr 04 01:36:45 PM PDT 24 |
15089900517 ps |
| T877 |
/workspace/coverage/default/17.sram_ctrl_stress_all_with_rand_reset.1040548312 |
|
|
Apr 04 01:41:51 PM PDT 24 |
Apr 04 01:42:05 PM PDT 24 |
2758079540 ps |
| T878 |
/workspace/coverage/default/18.sram_ctrl_throughput_w_partial_write.1859318852 |
|
|
Apr 04 01:42:14 PM PDT 24 |
Apr 04 01:42:22 PM PDT 24 |
2741643443 ps |
| T879 |
/workspace/coverage/default/13.sram_ctrl_alert_test.3448954980 |
|
|
Apr 04 01:39:29 PM PDT 24 |
Apr 04 01:39:30 PM PDT 24 |
46652410 ps |
| T880 |
/workspace/coverage/default/35.sram_ctrl_alert_test.43389362 |
|
|
Apr 04 01:55:06 PM PDT 24 |
Apr 04 01:55:07 PM PDT 24 |
10519141 ps |
| T881 |
/workspace/coverage/default/33.sram_ctrl_stress_pipeline.2306907780 |
|
|
Apr 04 01:53:26 PM PDT 24 |
Apr 04 01:57:20 PM PDT 24 |
14944192217 ps |
| T882 |
/workspace/coverage/default/8.sram_ctrl_mem_walk.1721423185 |
|
|
Apr 04 01:36:45 PM PDT 24 |
Apr 04 01:39:11 PM PDT 24 |
27544990449 ps |
| T883 |
/workspace/coverage/default/44.sram_ctrl_ram_cfg.3674284354 |
|
|
Apr 04 01:59:09 PM PDT 24 |
Apr 04 01:59:12 PM PDT 24 |
653671556 ps |
| T884 |
/workspace/coverage/default/19.sram_ctrl_throughput_w_partial_write.3602037375 |
|
|
Apr 04 01:42:44 PM PDT 24 |
Apr 04 01:43:21 PM PDT 24 |
5591947605 ps |
| T885 |
/workspace/coverage/default/31.sram_ctrl_regwen.1695420737 |
|
|
Apr 04 01:52:24 PM PDT 24 |
Apr 04 02:12:25 PM PDT 24 |
23165320437 ps |
| T886 |
/workspace/coverage/default/28.sram_ctrl_alert_test.1162492441 |
|
|
Apr 04 01:50:47 PM PDT 24 |
Apr 04 01:50:48 PM PDT 24 |
20199622 ps |
| T887 |
/workspace/coverage/default/49.sram_ctrl_alert_test.2034860494 |
|
|
Apr 04 02:00:57 PM PDT 24 |
Apr 04 02:00:58 PM PDT 24 |
18993189 ps |
| T888 |
/workspace/coverage/default/34.sram_ctrl_bijection.2732504070 |
|
|
Apr 04 01:53:53 PM PDT 24 |
Apr 04 02:19:00 PM PDT 24 |
23590478432 ps |
| T889 |
/workspace/coverage/default/40.sram_ctrl_stress_pipeline.332587300 |
|
|
Apr 04 01:57:47 PM PDT 24 |
Apr 04 02:00:42 PM PDT 24 |
6267771302 ps |
| T890 |
/workspace/coverage/default/46.sram_ctrl_access_during_key_req.2060310549 |
|
|
Apr 04 01:59:42 PM PDT 24 |
Apr 04 02:05:45 PM PDT 24 |
12868960433 ps |
| T891 |
/workspace/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2705200644 |
|
|
Apr 04 01:35:32 PM PDT 24 |
Apr 04 01:35:48 PM PDT 24 |
1877353971 ps |
| T892 |
/workspace/coverage/default/43.sram_ctrl_smoke.3923759788 |
|
|
Apr 04 01:58:34 PM PDT 24 |
Apr 04 02:00:16 PM PDT 24 |
1036007202 ps |
| T893 |
/workspace/coverage/default/13.sram_ctrl_bijection.313153262 |
|
|
Apr 04 01:39:03 PM PDT 24 |
Apr 04 02:17:19 PM PDT 24 |
135742535193 ps |
| T894 |
/workspace/coverage/default/32.sram_ctrl_partial_access_b2b.140017508 |
|
|
Apr 04 01:53:00 PM PDT 24 |
Apr 04 01:59:49 PM PDT 24 |
18246215428 ps |
| T895 |
/workspace/coverage/default/29.sram_ctrl_max_throughput.2380670444 |
|
|
Apr 04 01:50:58 PM PDT 24 |
Apr 04 01:51:27 PM PDT 24 |
744786039 ps |
| T896 |
/workspace/coverage/default/43.sram_ctrl_stress_all.2440664164 |
|
|
Apr 04 01:58:52 PM PDT 24 |
Apr 04 03:31:43 PM PDT 24 |
448993301141 ps |
| T897 |
/workspace/coverage/default/35.sram_ctrl_partial_access.2120513507 |
|
|
Apr 04 01:54:46 PM PDT 24 |
Apr 04 01:55:48 PM PDT 24 |
867607414 ps |
| T898 |
/workspace/coverage/default/37.sram_ctrl_multiple_keys.552455449 |
|
|
Apr 04 01:56:07 PM PDT 24 |
Apr 04 02:12:54 PM PDT 24 |
9498688578 ps |
| T899 |
/workspace/coverage/default/22.sram_ctrl_partial_access_b2b.2732660624 |
|
|
Apr 04 01:45:06 PM PDT 24 |
Apr 04 01:50:10 PM PDT 24 |
13810193769 ps |
| T900 |
/workspace/coverage/default/30.sram_ctrl_bijection.1303981818 |
|
|
Apr 04 01:51:19 PM PDT 24 |
Apr 04 02:21:08 PM PDT 24 |
83863604442 ps |
| T901 |
/workspace/coverage/default/34.sram_ctrl_regwen.2485252082 |
|
|
Apr 04 01:54:26 PM PDT 24 |
Apr 04 02:09:20 PM PDT 24 |
12904977683 ps |
| T902 |
/workspace/coverage/default/27.sram_ctrl_stress_all_with_rand_reset.136326298 |
|
|
Apr 04 01:49:25 PM PDT 24 |
Apr 04 01:49:39 PM PDT 24 |
878365215 ps |
| T903 |
/workspace/coverage/default/30.sram_ctrl_partial_access_b2b.2924222800 |
|
|
Apr 04 01:51:28 PM PDT 24 |
Apr 04 01:56:07 PM PDT 24 |
12572520107 ps |
| T904 |
/workspace/coverage/default/9.sram_ctrl_throughput_w_partial_write.3475555386 |
|
|
Apr 04 01:37:12 PM PDT 24 |
Apr 04 01:37:19 PM PDT 24 |
1366147099 ps |
| T905 |
/workspace/coverage/default/28.sram_ctrl_stress_pipeline.2235852726 |
|
|
Apr 04 01:50:13 PM PDT 24 |
Apr 04 01:54:12 PM PDT 24 |
7306090739 ps |
| T906 |
/workspace/coverage/default/8.sram_ctrl_partial_access.2896667581 |
|
|
Apr 04 01:36:45 PM PDT 24 |
Apr 04 01:36:54 PM PDT 24 |
1432132409 ps |
| T907 |
/workspace/coverage/default/47.sram_ctrl_max_throughput.3238020662 |
|
|
Apr 04 02:00:00 PM PDT 24 |
Apr 04 02:01:37 PM PDT 24 |
781267418 ps |
| T908 |
/workspace/coverage/default/23.sram_ctrl_ram_cfg.2804066615 |
|
|
Apr 04 01:45:54 PM PDT 24 |
Apr 04 01:45:57 PM PDT 24 |
1396566673 ps |
| T909 |
/workspace/coverage/default/30.sram_ctrl_partial_access.4256755086 |
|
|
Apr 04 01:51:28 PM PDT 24 |
Apr 04 01:51:39 PM PDT 24 |
2197967031 ps |
| T910 |
/workspace/coverage/default/48.sram_ctrl_multiple_keys.2115855898 |
|
|
Apr 04 02:00:21 PM PDT 24 |
Apr 04 02:18:48 PM PDT 24 |
47617208306 ps |
| T911 |
/workspace/coverage/default/18.sram_ctrl_partial_access.2224562195 |
|
|
Apr 04 01:42:03 PM PDT 24 |
Apr 04 01:42:19 PM PDT 24 |
14009574886 ps |
| T912 |
/workspace/coverage/default/20.sram_ctrl_executable.4188457792 |
|
|
Apr 04 01:43:28 PM PDT 24 |
Apr 04 01:55:58 PM PDT 24 |
14691069684 ps |
| T913 |
/workspace/coverage/default/8.sram_ctrl_partial_access_b2b.607523100 |
|
|
Apr 04 01:36:45 PM PDT 24 |
Apr 04 01:39:44 PM PDT 24 |
6733525604 ps |
| T914 |
/workspace/coverage/default/5.sram_ctrl_stress_all.1667998228 |
|
|
Apr 04 01:36:15 PM PDT 24 |
Apr 04 02:26:45 PM PDT 24 |
24917685832 ps |
| T915 |
/workspace/coverage/default/9.sram_ctrl_stress_pipeline.790309181 |
|
|
Apr 04 01:37:14 PM PDT 24 |
Apr 04 01:40:37 PM PDT 24 |
3643586193 ps |
| T916 |
/workspace/coverage/default/41.sram_ctrl_bijection.3284598627 |
|
|
Apr 04 01:57:56 PM PDT 24 |
Apr 04 02:34:59 PM PDT 24 |
546339146006 ps |
| T917 |
/workspace/coverage/default/48.sram_ctrl_max_throughput.1884397763 |
|
|
Apr 04 02:00:18 PM PDT 24 |
Apr 04 02:00:45 PM PDT 24 |
2653506097 ps |
| T918 |
/workspace/coverage/default/41.sram_ctrl_alert_test.951351795 |
|
|
Apr 04 01:58:14 PM PDT 24 |
Apr 04 01:58:15 PM PDT 24 |
48886751 ps |
| T919 |
/workspace/coverage/default/38.sram_ctrl_stress_pipeline.1953000079 |
|
|
Apr 04 01:56:41 PM PDT 24 |
Apr 04 01:59:33 PM PDT 24 |
12201541872 ps |
| T920 |
/workspace/coverage/default/14.sram_ctrl_multiple_keys.1375604382 |
|
|
Apr 04 01:39:32 PM PDT 24 |
Apr 04 01:53:30 PM PDT 24 |
8704213914 ps |
| T921 |
/workspace/coverage/default/22.sram_ctrl_bijection.2819475386 |
|
|
Apr 04 01:45:03 PM PDT 24 |
Apr 04 02:06:30 PM PDT 24 |
311512922022 ps |
| T922 |
/workspace/coverage/default/5.sram_ctrl_bijection.2833655261 |
|
|
Apr 04 01:35:55 PM PDT 24 |
Apr 04 02:10:51 PM PDT 24 |
31885651837 ps |
| T923 |
/workspace/coverage/default/31.sram_ctrl_stress_pipeline.2143966042 |
|
|
Apr 04 01:52:14 PM PDT 24 |
Apr 04 01:54:20 PM PDT 24 |
2610269724 ps |
| T924 |
/workspace/coverage/default/42.sram_ctrl_mem_walk.1578669750 |
|
|
Apr 04 01:58:33 PM PDT 24 |
Apr 04 02:02:35 PM PDT 24 |
16420428309 ps |
| T37 |
/workspace/coverage/default/1.sram_ctrl_sec_cm.4110234408 |
|
|
Apr 04 01:35:25 PM PDT 24 |
Apr 04 01:35:29 PM PDT 24 |
430699770 ps |
| T925 |
/workspace/coverage/default/11.sram_ctrl_mem_partial_access.3753089611 |
|
|
Apr 04 01:38:24 PM PDT 24 |
Apr 04 01:39:32 PM PDT 24 |
9089725236 ps |
| T926 |
/workspace/coverage/default/36.sram_ctrl_partial_access_b2b.1433635904 |
|
|
Apr 04 01:55:24 PM PDT 24 |
Apr 04 01:58:32 PM PDT 24 |
11137906360 ps |
| T927 |
/workspace/coverage/default/39.sram_ctrl_lc_escalation.1912236225 |
|
|
Apr 04 01:57:20 PM PDT 24 |
Apr 04 01:58:08 PM PDT 24 |
10500699355 ps |
| T928 |
/workspace/coverage/default/46.sram_ctrl_bijection.1143460997 |
|
|
Apr 04 01:59:42 PM PDT 24 |
Apr 04 02:25:21 PM PDT 24 |
94411065056 ps |
| T929 |
/workspace/coverage/default/26.sram_ctrl_stress_pipeline.2635533646 |
|
|
Apr 04 01:47:56 PM PDT 24 |
Apr 04 01:51:06 PM PDT 24 |
4489908526 ps |
| T930 |
/workspace/coverage/default/47.sram_ctrl_lc_escalation.2490681636 |
|
|
Apr 04 01:59:59 PM PDT 24 |
Apr 04 02:00:21 PM PDT 24 |
3673479766 ps |
| T931 |
/workspace/coverage/default/7.sram_ctrl_stress_all.599024035 |
|
|
Apr 04 01:36:34 PM PDT 24 |
Apr 04 01:53:54 PM PDT 24 |
34744775708 ps |
| T932 |
/workspace/coverage/default/40.sram_ctrl_partial_access_b2b.1623992070 |
|
|
Apr 04 01:57:46 PM PDT 24 |
Apr 04 02:02:53 PM PDT 24 |
24890845463 ps |
| T933 |
/workspace/coverage/default/7.sram_ctrl_access_during_key_req.1502952983 |
|
|
Apr 04 01:36:34 PM PDT 24 |
Apr 04 01:48:45 PM PDT 24 |
11459807507 ps |
| T934 |
/workspace/coverage/default/0.sram_ctrl_stress_all.2053128122 |
|
|
Apr 04 01:35:16 PM PDT 24 |
Apr 04 03:11:24 PM PDT 24 |
99764007688 ps |
| T935 |
/workspace/coverage/default/25.sram_ctrl_lc_escalation.2430347873 |
|
|
Apr 04 01:47:10 PM PDT 24 |
Apr 04 01:47:53 PM PDT 24 |
8094741188 ps |
| T936 |
/workspace/coverage/default/4.sram_ctrl_partial_access_b2b.1849831789 |
|
|
Apr 04 01:35:47 PM PDT 24 |
Apr 04 01:41:16 PM PDT 24 |
28311118669 ps |
| T937 |
/workspace/coverage/default/11.sram_ctrl_smoke.4172513808 |
|
|
Apr 04 01:37:54 PM PDT 24 |
Apr 04 01:38:03 PM PDT 24 |
424690295 ps |
| T938 |
/workspace/coverage/default/2.sram_ctrl_mem_partial_access.1224636795 |
|
|
Apr 04 01:35:39 PM PDT 24 |
Apr 04 01:37:38 PM PDT 24 |
11042476846 ps |
| T939 |
/workspace/coverage/default/12.sram_ctrl_max_throughput.1783343166 |
|
|
Apr 04 01:38:31 PM PDT 24 |
Apr 04 01:38:38 PM PDT 24 |
2690298723 ps |
| T940 |
/workspace/coverage/default/16.sram_ctrl_mem_walk.4167008932 |
|
|
Apr 04 01:41:16 PM PDT 24 |
Apr 04 01:45:09 PM PDT 24 |
8207647268 ps |
| T941 |
/workspace/coverage/default/13.sram_ctrl_partial_access.176919058 |
|
|
Apr 04 01:39:04 PM PDT 24 |
Apr 04 01:40:09 PM PDT 24 |
838598631 ps |
| T942 |
/workspace/coverage/default/12.sram_ctrl_partial_access.3075806054 |
|
|
Apr 04 01:38:33 PM PDT 24 |
Apr 04 01:38:45 PM PDT 24 |
2728674796 ps |
| T943 |
/workspace/coverage/default/40.sram_ctrl_stress_all_with_rand_reset.3474316451 |
|
|
Apr 04 01:57:46 PM PDT 24 |
Apr 04 02:00:38 PM PDT 24 |
28085298137 ps |
| T38 |
/workspace/coverage/default/2.sram_ctrl_sec_cm.1967922933 |
|
|
Apr 04 01:35:36 PM PDT 24 |
Apr 04 01:35:38 PM PDT 24 |
158649501 ps |
| T944 |
/workspace/coverage/default/22.sram_ctrl_stress_all.44442385 |
|
|
Apr 04 01:45:33 PM PDT 24 |
Apr 04 02:33:28 PM PDT 24 |
251735354315 ps |
| T67 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3472720231 |
|
|
Apr 04 02:56:20 PM PDT 24 |
Apr 04 02:56:21 PM PDT 24 |
65215968 ps |
| T104 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_passthru_mem_tl_intg_err.1839685981 |
|
|
Apr 04 02:56:53 PM PDT 24 |
Apr 04 02:57:21 PM PDT 24 |
10048278810 ps |
| T114 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2783582893 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:33 PM PDT 24 |
442776902 ps |
| T105 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_same_csr_outstanding.3950037748 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:32 PM PDT 24 |
30819452 ps |
| T106 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_rw.2926442563 |
|
|
Apr 04 02:56:43 PM PDT 24 |
Apr 04 02:56:43 PM PDT 24 |
37404805 ps |
| T115 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.4162848956 |
|
|
Apr 04 02:56:56 PM PDT 24 |
Apr 04 02:56:58 PM PDT 24 |
1246688294 ps |
| T945 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2349201424 |
|
|
Apr 04 02:56:18 PM PDT 24 |
Apr 04 02:56:25 PM PDT 24 |
733447751 ps |
| T946 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_hw_reset.2937986657 |
|
|
Apr 04 02:56:33 PM PDT 24 |
Apr 04 02:56:33 PM PDT 24 |
18965284 ps |
| T116 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.1282463156 |
|
|
Apr 04 02:56:34 PM PDT 24 |
Apr 04 02:56:36 PM PDT 24 |
199933306 ps |
| T68 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_same_csr_outstanding.3633112018 |
|
|
Apr 04 02:56:48 PM PDT 24 |
Apr 04 02:56:49 PM PDT 24 |
25408286 ps |
| T69 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_csr_rw.3315637605 |
|
|
Apr 04 02:56:48 PM PDT 24 |
Apr 04 02:56:48 PM PDT 24 |
34698638 ps |
| T70 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_rw.2106421530 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:56:36 PM PDT 24 |
68755827 ps |
| T947 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_mem_rw_with_rand_reset.3835855762 |
|
|
Apr 04 02:57:07 PM PDT 24 |
Apr 04 02:57:11 PM PDT 24 |
1756577570 ps |
| T71 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_rw.712625973 |
|
|
Apr 04 02:56:56 PM PDT 24 |
Apr 04 02:56:57 PM PDT 24 |
42250247 ps |
| T948 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_errors.2519818536 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:36 PM PDT 24 |
302236709 ps |
| T72 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_csr_rw.180868676 |
|
|
Apr 04 02:56:20 PM PDT 24 |
Apr 04 02:56:20 PM PDT 24 |
13802490 ps |
| T949 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_tl_errors.1645448676 |
|
|
Apr 04 02:56:36 PM PDT 24 |
Apr 04 02:56:39 PM PDT 24 |
81768632 ps |
| T113 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2503292770 |
|
|
Apr 04 02:56:16 PM PDT 24 |
Apr 04 02:56:17 PM PDT 24 |
13393027 ps |
| T950 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_csr_mem_rw_with_rand_reset.994204896 |
|
|
Apr 04 02:56:58 PM PDT 24 |
Apr 04 02:57:01 PM PDT 24 |
354288601 ps |
| T951 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_tl_errors.3326520762 |
|
|
Apr 04 02:56:40 PM PDT 24 |
Apr 04 02:56:43 PM PDT 24 |
73154223 ps |
| T125 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.1804354889 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
372837281 ps |
| T73 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_hw_reset.3372210870 |
|
|
Apr 04 02:56:39 PM PDT 24 |
Apr 04 02:56:40 PM PDT 24 |
28656393 ps |
| T131 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.1189902209 |
|
|
Apr 04 02:56:30 PM PDT 24 |
Apr 04 02:56:31 PM PDT 24 |
74374369 ps |
| T74 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_passthru_mem_tl_intg_err.1398046689 |
|
|
Apr 04 02:56:37 PM PDT 24 |
Apr 04 02:57:22 PM PDT 24 |
50696239235 ps |
| T75 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_passthru_mem_tl_intg_err.732131584 |
|
|
Apr 04 02:56:51 PM PDT 24 |
Apr 04 02:57:22 PM PDT 24 |
15408321940 ps |
| T126 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.3760077924 |
|
|
Apr 04 02:56:42 PM PDT 24 |
Apr 04 02:56:44 PM PDT 24 |
704943768 ps |
| T76 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.3032759048 |
|
|
Apr 04 02:56:26 PM PDT 24 |
Apr 04 02:56:32 PM PDT 24 |
64205014 ps |
| T952 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_same_csr_outstanding.1708966089 |
|
|
Apr 04 02:56:30 PM PDT 24 |
Apr 04 02:56:31 PM PDT 24 |
21059875 ps |
| T953 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_errors.325135247 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
29990437 ps |
| T954 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.3986625272 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:33 PM PDT 24 |
53627623 ps |
| T955 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_aliasing.2036783559 |
|
|
Apr 04 02:56:34 PM PDT 24 |
Apr 04 02:56:35 PM PDT 24 |
306579793 ps |
| T956 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1623248974 |
|
|
Apr 04 02:56:37 PM PDT 24 |
Apr 04 02:56:40 PM PDT 24 |
6809663883 ps |
| T957 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_tl_errors.1253471437 |
|
|
Apr 04 02:56:50 PM PDT 24 |
Apr 04 02:56:54 PM PDT 24 |
503028417 ps |
| T78 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_rw.2111110118 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:32 PM PDT 24 |
23146914 ps |
| T958 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_same_csr_outstanding.2205421152 |
|
|
Apr 04 02:56:23 PM PDT 24 |
Apr 04 02:56:23 PM PDT 24 |
29112365 ps |
| T79 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_rw.4094409705 |
|
|
Apr 04 02:56:16 PM PDT 24 |
Apr 04 02:56:22 PM PDT 24 |
37221038 ps |
| T959 |
/workspace/coverage/cover_reg_top/10.sram_ctrl_csr_rw.3325214123 |
|
|
Apr 04 02:56:38 PM PDT 24 |
Apr 04 02:56:38 PM PDT 24 |
27724426 ps |
| T960 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1178087047 |
|
|
Apr 04 02:56:39 PM PDT 24 |
Apr 04 02:56:43 PM PDT 24 |
152938144 ps |
| T961 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_mem_rw_with_rand_reset.2802349442 |
|
|
Apr 04 02:56:30 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
364688923 ps |
| T962 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.2008895819 |
|
|
Apr 04 02:56:16 PM PDT 24 |
Apr 04 02:56:52 PM PDT 24 |
52781203111 ps |
| T963 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_same_csr_outstanding.1907668376 |
|
|
Apr 04 02:56:27 PM PDT 24 |
Apr 04 02:56:28 PM PDT 24 |
48028156 ps |
| T964 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_hw_reset.3538053226 |
|
|
Apr 04 02:56:27 PM PDT 24 |
Apr 04 02:56:28 PM PDT 24 |
24467436 ps |
| T965 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.3032222670 |
|
|
Apr 04 02:56:21 PM PDT 24 |
Apr 04 02:56:25 PM PDT 24 |
750445489 ps |
| T128 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1620084737 |
|
|
Apr 04 02:56:11 PM PDT 24 |
Apr 04 02:56:14 PM PDT 24 |
868720847 ps |
| T966 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_rw.842549642 |
|
|
Apr 04 02:56:42 PM PDT 24 |
Apr 04 02:56:43 PM PDT 24 |
53861164 ps |
| T967 |
/workspace/coverage/cover_reg_top/17.sram_ctrl_csr_rw.2139712796 |
|
|
Apr 04 02:56:54 PM PDT 24 |
Apr 04 02:56:55 PM PDT 24 |
42924277 ps |
| T968 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_bit_bash.1189808765 |
|
|
Apr 04 02:56:36 PM PDT 24 |
Apr 04 02:56:38 PM PDT 24 |
332119357 ps |
| T969 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_same_csr_outstanding.1717425803 |
|
|
Apr 04 02:56:53 PM PDT 24 |
Apr 04 02:56:54 PM PDT 24 |
26186296 ps |
| T970 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_same_csr_outstanding.1654259590 |
|
|
Apr 04 02:56:34 PM PDT 24 |
Apr 04 02:56:35 PM PDT 24 |
49633797 ps |
| T80 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.3462794138 |
|
|
Apr 04 02:56:11 PM PDT 24 |
Apr 04 02:57:05 PM PDT 24 |
29435879215 ps |
| T81 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_passthru_mem_tl_intg_err.1169385812 |
|
|
Apr 04 02:56:47 PM PDT 24 |
Apr 04 02:57:15 PM PDT 24 |
3898913341 ps |
| T971 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_hw_reset.1951093997 |
|
|
Apr 04 02:56:15 PM PDT 24 |
Apr 04 02:56:15 PM PDT 24 |
26012523 ps |
| T972 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_csr_mem_rw_with_rand_reset.939331541 |
|
|
Apr 04 02:56:53 PM PDT 24 |
Apr 04 02:56:57 PM PDT 24 |
377226575 ps |
| T973 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_errors.3709098654 |
|
|
Apr 04 02:56:10 PM PDT 24 |
Apr 04 02:56:12 PM PDT 24 |
70013839 ps |
| T974 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_mem_rw_with_rand_reset.3116076504 |
|
|
Apr 04 02:56:36 PM PDT 24 |
Apr 04 02:56:40 PM PDT 24 |
712221517 ps |
| T975 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_csr_mem_rw_with_rand_reset.1306111428 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:56:39 PM PDT 24 |
364809742 ps |
| T976 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4248018085 |
|
|
Apr 04 02:56:27 PM PDT 24 |
Apr 04 02:56:28 PM PDT 24 |
123300592 ps |
| T82 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_bit_bash.3985656160 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:35 PM PDT 24 |
593169996 ps |
| T977 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_csr_mem_rw_with_rand_reset.7381964 |
|
|
Apr 04 02:56:40 PM PDT 24 |
Apr 04 02:56:44 PM PDT 24 |
697182354 ps |
| T129 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2798022580 |
|
|
Apr 04 02:56:33 PM PDT 24 |
Apr 04 02:56:35 PM PDT 24 |
690760666 ps |
| T94 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_passthru_mem_tl_intg_err.798913514 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:57:02 PM PDT 24 |
3750033434 ps |
| T83 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_passthru_mem_tl_intg_err.53292217 |
|
|
Apr 04 02:56:48 PM PDT 24 |
Apr 04 02:57:41 PM PDT 24 |
14100121023 ps |
| T978 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_csr_rw.2153761881 |
|
|
Apr 04 02:56:33 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
30947399 ps |
| T979 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_bit_bash.2545996861 |
|
|
Apr 04 02:57:26 PM PDT 24 |
Apr 04 02:57:29 PM PDT 24 |
161962416 ps |
| T980 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_same_csr_outstanding.1883082346 |
|
|
Apr 04 02:56:26 PM PDT 24 |
Apr 04 02:56:26 PM PDT 24 |
18943932 ps |
| T84 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_aliasing.4005190756 |
|
|
Apr 04 02:56:30 PM PDT 24 |
Apr 04 02:56:30 PM PDT 24 |
13741397 ps |
| T981 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_csr_bit_bash.2271422881 |
|
|
Apr 04 02:56:15 PM PDT 24 |
Apr 04 02:56:17 PM PDT 24 |
156689180 ps |
| T982 |
/workspace/coverage/cover_reg_top/13.sram_ctrl_csr_rw.1455469758 |
|
|
Apr 04 02:56:58 PM PDT 24 |
Apr 04 02:56:59 PM PDT 24 |
15781467 ps |
| T130 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3608310900 |
|
|
Apr 04 02:56:13 PM PDT 24 |
Apr 04 02:56:15 PM PDT 24 |
291068748 ps |
| T983 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_passthru_mem_tl_intg_err.3322547046 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:57:07 PM PDT 24 |
15416893790 ps |
| T95 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2865452846 |
|
|
Apr 04 02:56:10 PM PDT 24 |
Apr 04 02:57:10 PM PDT 24 |
30660462272 ps |
| T984 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_csr_rw.1934105925 |
|
|
Apr 04 02:56:33 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
48393207 ps |
| T985 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_rw.789936687 |
|
|
Apr 04 02:56:43 PM PDT 24 |
Apr 04 02:56:43 PM PDT 24 |
30193275 ps |
| T986 |
/workspace/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3984438899 |
|
|
Apr 04 02:56:54 PM PDT 24 |
Apr 04 02:56:57 PM PDT 24 |
251166180 ps |
| T987 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_same_csr_outstanding.43180794 |
|
|
Apr 04 02:56:44 PM PDT 24 |
Apr 04 02:56:45 PM PDT 24 |
32327378 ps |
| T988 |
/workspace/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.4275028519 |
|
|
Apr 04 02:56:25 PM PDT 24 |
Apr 04 02:56:27 PM PDT 24 |
953213038 ps |
| T989 |
/workspace/coverage/cover_reg_top/19.sram_ctrl_same_csr_outstanding.2531230563 |
|
|
Apr 04 02:56:51 PM PDT 24 |
Apr 04 02:56:52 PM PDT 24 |
80798405 ps |
| T990 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2540911503 |
|
|
Apr 04 02:56:33 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
83417563 ps |
| T991 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.2994663447 |
|
|
Apr 04 02:56:24 PM PDT 24 |
Apr 04 02:56:28 PM PDT 24 |
4345706089 ps |
| T992 |
/workspace/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1480820707 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:56:33 PM PDT 24 |
138324420 ps |
| T993 |
/workspace/coverage/cover_reg_top/15.sram_ctrl_csr_rw.1852044428 |
|
|
Apr 04 02:56:50 PM PDT 24 |
Apr 04 02:56:50 PM PDT 24 |
12088645 ps |
| T994 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.1907412579 |
|
|
Apr 04 02:56:31 PM PDT 24 |
Apr 04 02:57:21 PM PDT 24 |
7658356071 ps |
| T995 |
/workspace/coverage/cover_reg_top/8.sram_ctrl_csr_mem_rw_with_rand_reset.4012063623 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:56:39 PM PDT 24 |
1492638082 ps |
| T996 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_tl_errors.998633992 |
|
|
Apr 04 02:56:34 PM PDT 24 |
Apr 04 02:56:37 PM PDT 24 |
131713958 ps |
| T132 |
/workspace/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.3393139146 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
245307963 ps |
| T997 |
/workspace/coverage/cover_reg_top/5.sram_ctrl_csr_mem_rw_with_rand_reset.1862948544 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:36 PM PDT 24 |
368413056 ps |
| T133 |
/workspace/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.417560446 |
|
|
Apr 04 02:56:32 PM PDT 24 |
Apr 04 02:56:34 PM PDT 24 |
159473535 ps |
| T135 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.2443135333 |
|
|
Apr 04 02:56:46 PM PDT 24 |
Apr 04 02:56:49 PM PDT 24 |
161074844 ps |
| T998 |
/workspace/coverage/cover_reg_top/0.sram_ctrl_tl_errors.2661532618 |
|
|
Apr 04 02:56:25 PM PDT 24 |
Apr 04 02:56:27 PM PDT 24 |
27596788 ps |
| T999 |
/workspace/coverage/cover_reg_top/18.sram_ctrl_csr_mem_rw_with_rand_reset.2890471554 |
|
|
Apr 04 02:56:54 PM PDT 24 |
Apr 04 02:56:59 PM PDT 24 |
7047941819 ps |
| T134 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.3812812097 |
|
|
Apr 04 02:56:36 PM PDT 24 |
Apr 04 02:56:38 PM PDT 24 |
600262079 ps |
| T1000 |
/workspace/coverage/cover_reg_top/9.sram_ctrl_passthru_mem_tl_intg_err.673733868 |
|
|
Apr 04 02:56:35 PM PDT 24 |
Apr 04 02:57:01 PM PDT 24 |
7771828617 ps |
| T1001 |
/workspace/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.324815255 |
|
|
Apr 04 02:56:56 PM PDT 24 |
Apr 04 02:56:57 PM PDT 24 |
163397136 ps |
| T1002 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_csr_aliasing.3490775877 |
|
|
Apr 04 02:56:19 PM PDT 24 |
Apr 04 02:56:20 PM PDT 24 |
31082880 ps |
| T1003 |
/workspace/coverage/cover_reg_top/3.sram_ctrl_tl_errors.1913514121 |
|
|
Apr 04 02:56:21 PM PDT 24 |
Apr 04 02:56:24 PM PDT 24 |
27803840 ps |
| T136 |
/workspace/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3313164951 |
|
|
Apr 04 02:56:41 PM PDT 24 |
Apr 04 02:56:44 PM PDT 24 |
301536189 ps |
| T1004 |
/workspace/coverage/cover_reg_top/12.sram_ctrl_tl_errors.3573959819 |
|
|
Apr 04 02:56:57 PM PDT 24 |
Apr 04 02:57:01 PM PDT 24 |
468237555 ps |
| T1005 |
/workspace/coverage/cover_reg_top/2.sram_ctrl_csr_aliasing.2521623816 |
|
|
Apr 04 02:56:21 PM PDT 24 |
Apr 04 02:56:32 PM PDT 24 |
28403217 ps |