Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15689353

1

T1

3158

T3

59542

T4

6651

full_word

154961842

1

T1

3906

T2

98303

T3

3199

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	170650875	1			T1	7064		T2	98303		T3	62741
auto[TlIntgErrCmd]	101	1			T99	6		T100	3		T101	5
auto[TlIntgErrData]	111	1			T99	4		T100	11		T101	4
auto[TlIntgErrBoth]	108	1			T99	10		T100	6		T101	1

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82312196

1

T1

1576

T2

32768

T3

31468

auto[1]

88338999

1

T1

5488

T2

65535

T3

31273

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7670873	1			T1	600		T3	31206		T4	1495
auto[TlIntgErrNone]	partial	auto[1]	8018191	1			T1	2558		T3	28336		T4	5156
auto[TlIntgErrNone]	full_word	auto[0]	74641175	1			T1	976		T2	32768		T3	262
auto[TlIntgErrNone]	full_word	auto[1]	80320636	1			T1	2930		T2	65535		T3	2937
auto[TlIntgErrCmd]	partial	auto[0]	39	1			T99	3		T101	4		T125	2
auto[TlIntgErrCmd]	partial	auto[1]	51	1			T99	3		T100	2		T101	1
auto[TlIntgErrCmd]	full_word	auto[0]	6	1			T125	1		T128	1		T127	2
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T100	1		T129	1		T130	1
auto[TlIntgErrData]	partial	auto[0]	50	1			T99	1		T100	5		T101	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T99	2		T100	6		T101	3
auto[TlIntgErrData]	full_word	auto[0]	8	1			T99	1		T125	2		T126	1
auto[TlIntgErrData]	full_word	auto[1]	5	1			T123	1		T130	1		T131	1
auto[TlIntgErrBoth]	partial	auto[0]	42	1			T99	3		T100	1		T125	2
auto[TlIntgErrBoth]	partial	auto[1]	59	1			T99	7		T100	5		T101	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T129	1		T124	1		T132	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1			T125	1		T122	1		T131	1