Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	642046	1			T6	24		T13	6		T14	137
auto[1]	11339210	1			T3	28669		T4	509		T5	43931
auto[2]	504356	1			T6	12		T13	3		T14	94
auto[3]	11073864	1			T3	28422		T4	573		T5	43474

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	14423884	1			T3	307		T4	907		T5	72571
auto[1]	2226386	1			T3	2864		T4	90		T5	6972
auto[2]	2248683	1			T3	5467		T4	76		T5	7125
auto[3]	4660523	1			T3	48453		T4	9		T5	737

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10121519

1

T3

57090

T4

1082

T5

87402

auto[1]

13437957

1

T3

1

T5

3

T11

1

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	268629	1			T6	21		T13	5		T14	115
auto[0]	auto[0]	auto[1]	28605	1			T14	12		T8	757		T43	111
auto[0]	auto[0]	auto[2]	28876	1			T6	2		T13	1		T14	9
auto[0]	auto[0]	auto[3]	105356	1			T6	1		T14	1		T8	73
auto[0]	auto[1]	auto[0]	3548791	1			T3	33		T4	425		T5	36412
auto[0]	auto[1]	auto[1]	371019	1			T3	201		T4	39		T5	3502
auto[0]	auto[1]	auto[2]	389804	1			T3	3081		T4	41		T5	3655
auto[0]	auto[1]	auto[3]	488092	1			T3	25354		T4	4		T5	359
auto[0]	auto[2]	auto[0]	207685	1			T6	12		T13	2		T14	62
auto[0]	auto[2]	auto[1]	30011	1			T13	1		T14	10		T8	444
auto[0]	auto[2]	auto[2]	20449	1			T14	20		T8	312		T43	98
auto[0]	auto[2]	auto[3]	70331	1			T14	2		T8	34		T43	10
auto[0]	auto[3]	auto[0]	3379758	1			T3	274		T4	482		T5	36158
auto[0]	auto[3]	auto[1]	368772	1			T3	2663		T4	51		T5	3468
auto[0]	auto[3]	auto[2]	383965	1			T3	2386		T4	35		T5	3470
auto[0]	auto[3]	auto[3]	431376	1			T3	23098		T4	5		T5	378
auto[1]	auto[0]	auto[0]	7135	1			T137	1		T136	574		T138	1
auto[1]	auto[0]	auto[1]	31368	1			T136	2435		T41	1568		T139	2971
auto[1]	auto[0]	auto[2]	31341	1			T136	2507		T41	1603		T139	2908
auto[1]	auto[0]	auto[3]	140736	1			T85	1		T140	1		T136	10981
auto[1]	auto[1]	auto[0]	3504440	1			T5	1		T11	1		T55	1
auto[1]	auto[1]	auto[1]	692349	1			T5	2		T68	6662		T89	9617
auto[1]	auto[1]	auto[2]	681242	1			T68	7347		T89	10558		T90	8840
auto[1]	auto[1]	auto[3]	1663473	1			T68	679		T89	43773		T90	794
auto[1]	auto[2]	auto[0]	6034	1			T136	524		T41	218		T139	625
auto[1]	auto[2]	auto[1]	26910	1			T136	2109		T41	947		T139	2784
auto[1]	auto[2]	auto[2]	26069	1			T136	2024		T41	1760		T139	2497
auto[1]	auto[2]	auto[3]	116867	1			T136	9156		T41	7896		T139	11120
auto[1]	auto[3]	auto[0]	3501412	1			T68	74380		T89	2341		T90	87122
auto[1]	auto[3]	auto[1]	677352	1			T68	7370		T89	10903		T90	8664
auto[1]	auto[3]	auto[2]	686937	1			T68	6694		T89	9784		T90	7802
auto[1]	auto[3]	auto[3]	1644292	1			T3	1		T68	649		T89	43763