Unified Coverage Report :: Module :: sram_ctrl_regs_csr_assert_fpv

Module : sram_ctrl_regs_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sram_ctrl_csr_assert_0/sram_ctrl_regs_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sram_ctrl_regs_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sram_ctrl_regs_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.26	100.00	94.62	100.00		100.00	91.67	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sram_ctrl_regs_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1081129089	138425	0	0
ctrl_regwen_rd_A	1081129089	6549	0	0
exec_rd_A	1081129089	5911	0	0
exec_regwen_rd_A	1081129089	6475	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081129089	138425	0	0
T1	53766	1624	0	0
T2	197205	0	0	0
T3	156389	0	0	0
T4	111484	3600	0	0
T5	120140	0	0	0
T6	586855	0	0	0
T9	514658	0	0	0
T10	106991	0	0	0
T11	281580	0	0	0
T12	68583	0	0	0
T29	0	1138	0	0
T45	0	2829	0	0
T46	0	684	0	0
T47	0	1157	0	0
T48	0	8110	0	0
T49	0	1477	0	0
T50	0	877	0	0
T51	0	4856	0	0

ctrl_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081129089	6549	0	0
T102	154858	691	0	0
T103	0	476	0	0
T104	0	581	0	0
T105	0	311	0	0
T106	0	323	0	0
T107	0	207	0	0
T108	0	410	0	0
T109	0	420	0	0
T110	0	271	0	0
T111	0	221	0	0
T112	510881	0	0	0
T113	119024	0	0	0
T114	34219	0	0	0
T115	65862	0	0	0
T116	499128	0	0	0
T117	542243	0	0	0
T118	101921	0	0	0
T119	1430	0	0	0
T120	846904	0	0	0

exec_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081129089	5911	0	0
T102	154858	525	0	0
T103	0	424	0	0
T104	0	489	0	0
T105	0	281	0	0
T106	0	288	0	0
T107	0	202	0	0
T108	0	318	0	0
T109	0	293	0	0
T110	0	258	0	0
T111	0	191	0	0
T112	510881	0	0	0
T113	119024	0	0	0
T114	34219	0	0	0
T115	65862	0	0	0
T116	499128	0	0	0
T117	542243	0	0	0
T118	101921	0	0	0
T119	1430	0	0	0
T120	846904	0	0	0

exec_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1081129089	6475	0	0
T102	154858	721	0	0
T103	0	485	0	0
T104	0	512	0	0
T105	0	261	0	0
T106	0	307	0	0
T107	0	180	0	0
T108	0	375	0	0
T109	0	411	0	0
T110	0	271	0	0
T111	0	204	0	0
T112	510881	0	0	0
T113	119024	0	0	0
T114	34219	0	0	0
T115	65862	0	0	0
T116	499128	0	0	0
T117	542243	0	0	0
T118	101921	0	0	0
T119	1430	0	0	0
T120	846904	0	0	0