Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_prim_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sram_ctrl_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	16071311	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

157190520

1

T1

1890

T3

2476

T4

8647

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	85299852	1			T1	1125		T3	1419		T4	4869
values[0x0]	42375958	1			T1	550		T3	626		T4	2243
values[0x1]	45586021	1			T1	617		T3	672		T4	2426

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8185893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

165075938

1

T1

2092

T3

2592

T4

9095

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	560268	1			T1	2		T5	63		T8	221
valid_sources[0x01]	580758	1			T1	8		T3	1		T5	45
valid_sources[0x02]	1821202	1			T1	7		T3	60		T5	28
valid_sources[0x03]	539529	1			T1	9		T5	27		T8	230
valid_sources[0x04]	626520	1			T1	9		T5	23		T8	237
valid_sources[0x05]	585206	1			T1	9		T5	43		T8	254
valid_sources[0x06]	648126	1			T1	7		T3	83		T5	34
valid_sources[0x07]	626662	1			T1	5		T3	45		T5	37
valid_sources[0x08]	517333	1			T1	11		T3	2		T5	62
valid_sources[0x09]	562642	1			T1	5		T5	47		T8	270
valid_sources[0x0a]	543471	1			T1	7		T5	34		T8	252
valid_sources[0x0b]	2621502	1			T1	17		T5	40		T8	249
valid_sources[0x0c]	545161	1			T1	14		T3	1		T5	28
valid_sources[0x0d]	518176	1			T1	5		T5	33		T8	260
valid_sources[0x0e]	569849	1			T1	8		T5	39		T8	255
valid_sources[0x0f]	727912	1			T1	9		T5	29		T8	223
valid_sources[0x10]	533085	1			T1	7		T3	1		T5	50
valid_sources[0x11]	615237	1			T1	5		T5	46		T8	276
valid_sources[0x12]	558270	1			T1	7		T5	40		T8	252
valid_sources[0x13]	539145	1			T1	14		T5	14		T8	238
valid_sources[0x14]	607378	1			T1	9		T5	48		T8	236
valid_sources[0x15]	517980	1			T1	5		T5	48		T8	213
valid_sources[0x16]	556713	1			T1	13		T5	18		T8	245
valid_sources[0x17]	536835	1			T1	4		T5	13		T8	234
valid_sources[0x18]	545977	1			T1	6		T5	14		T8	251
valid_sources[0x19]	763789	1			T1	7		T5	53		T8	277
valid_sources[0x1a]	524368	1			T1	6		T3	122		T5	34
valid_sources[0x1b]	590603	1			T1	5		T5	67		T8	300
valid_sources[0x1c]	1631240	1			T1	3		T3	3		T5	33
valid_sources[0x1d]	621365	1			T1	3		T5	22		T8	253
valid_sources[0x1e]	963985	1			T1	15		T5	35		T8	277
valid_sources[0x1f]	540883	1			T1	10		T3	9		T5	42
valid_sources[0x20]	530038	1			T1	15		T5	43		T8	230
valid_sources[0x21]	528174	1			T1	10		T5	30		T8	239
valid_sources[0x22]	1543258	1			T1	7		T5	57		T8	207
valid_sources[0x23]	525946	1			T1	13		T3	81		T5	30
valid_sources[0x24]	520090	1			T1	12		T5	61		T8	225
valid_sources[0x25]	534867	1			T1	5		T5	20		T8	227
valid_sources[0x26]	574076	1			T1	7		T5	12		T8	254
valid_sources[0x27]	539531	1			T1	11		T5	76		T8	247
valid_sources[0x28]	2305629	1			T1	10		T5	53		T8	227
valid_sources[0x29]	532510	1			T1	19		T5	50		T8	230
valid_sources[0x2a]	523468	1			T1	6		T5	53		T8	218
valid_sources[0x2b]	576182	1			T1	14		T5	69		T8	248
valid_sources[0x2c]	575692	1			T1	10		T3	117		T5	36
valid_sources[0x2d]	520521	1			T1	11		T5	57		T8	287
valid_sources[0x2e]	520373	1			T1	9		T3	15		T5	32
valid_sources[0x2f]	523669	1			T1	7		T5	24		T8	227
valid_sources[0x30]	639563	1			T1	7		T5	81		T8	235
valid_sources[0x31]	591905	1			T1	11		T3	19		T5	34
valid_sources[0x32]	581761	1			T1	14		T3	37		T5	40
valid_sources[0x33]	583191	1			T1	11		T5	34		T8	250
valid_sources[0x34]	519509	1			T1	5		T3	3		T5	13
valid_sources[0x35]	636802	1			T1	10		T5	37		T8	257
valid_sources[0x36]	553288	1			T1	11		T3	44		T5	25
valid_sources[0x37]	538647	1			T1	14		T5	22		T8	217
valid_sources[0x38]	578290	1			T1	5		T5	56		T8	225
valid_sources[0x39]	528534	1			T1	15		T5	21		T8	188
valid_sources[0x3a]	2090041	1			T1	5		T5	33		T8	274
valid_sources[0x3b]	534725	1			T1	4		T5	40		T8	249
valid_sources[0x3c]	576134	1			T1	12		T5	9		T8	245
valid_sources[0x3d]	585332	1			T1	10		T5	23		T8	226
valid_sources[0x3e]	570129	1			T1	7		T5	43		T8	236
valid_sources[0x3f]	561061	1			T1	8		T3	27		T5	23
valid_sources[0x40]	522724	1			T1	14		T5	38		T8	247
valid_sources[0x41]	523427	1			T1	2		T5	19		T8	242
valid_sources[0x42]	531556	1			T1	12		T5	38		T8	236
valid_sources[0x43]	558931	1			T1	9		T5	23		T8	234
valid_sources[0x44]	1712363	1			T1	9		T3	76		T5	69
valid_sources[0x45]	525255	1			T1	9		T3	51		T5	37
valid_sources[0x46]	547399	1			T1	6		T5	31		T8	270
valid_sources[0x47]	577793	1			T1	11		T5	51		T8	257
valid_sources[0x48]	613171	1			T1	12		T3	16		T5	23
valid_sources[0x49]	722356	1			T1	13		T5	29		T8	225
valid_sources[0x4a]	583110	1			T1	9		T3	19		T5	32
valid_sources[0x4b]	518193	1			T1	10		T5	17		T8	244
valid_sources[0x4c]	523303	1			T1	8		T3	116		T5	20
valid_sources[0x4d]	533067	1			T1	12		T5	32		T8	239
valid_sources[0x4e]	578883	1			T1	13		T3	47		T5	13
valid_sources[0x4f]	548190	1			T1	10		T5	21		T8	277
valid_sources[0x50]	560434	1			T1	6		T5	57		T8	218
valid_sources[0x51]	552150	1			T1	11		T5	37		T8	285
valid_sources[0x52]	522211	1			T1	4		T5	63		T8	227
valid_sources[0x53]	545265	1			T1	11		T5	35		T8	206
valid_sources[0x54]	526395	1			T1	10		T3	32		T5	23
valid_sources[0x55]	567815	1			T1	4		T5	68		T8	255
valid_sources[0x56]	549033	1			T1	7		T5	40		T8	249
valid_sources[0x57]	527459	1			T1	19		T5	47		T8	231
valid_sources[0x58]	731737	1			T1	11		T5	80		T8	245
valid_sources[0x59]	581128	1			T1	8		T3	13		T5	37
valid_sources[0x5a]	541988	1			T1	14		T5	49		T8	253
valid_sources[0x5b]	2164411	1			T1	11		T5	40		T8	229
valid_sources[0x5c]	1258030	1			T1	5		T5	34		T8	212
valid_sources[0x5d]	552545	1			T1	10		T5	70		T8	253
valid_sources[0x5e]	631200	1			T1	5		T5	21		T8	204
valid_sources[0x5f]	552250	1			T1	12		T3	30		T5	26
valid_sources[0x60]	521004	1			T1	9		T5	39		T8	186
valid_sources[0x61]	520538	1			T1	12		T5	30		T8	258
valid_sources[0x62]	556655	1			T1	8		T5	35		T8	211
valid_sources[0x63]	593421	1			T1	8		T5	36		T8	263
valid_sources[0x64]	532267	1			T1	4		T5	25		T8	231
valid_sources[0x65]	523130	1			T1	12		T3	19		T5	18
valid_sources[0x66]	560479	1			T1	6		T5	23		T8	227
valid_sources[0x67]	572914	1			T1	8		T5	44		T8	258
valid_sources[0x68]	519801	1			T1	11		T5	99		T8	267
valid_sources[0x69]	556557	1			T1	11		T5	34		T8	277
valid_sources[0x6a]	526174	1			T1	2		T3	28		T5	43
valid_sources[0x6b]	537082	1			T1	9		T5	24		T8	259
valid_sources[0x6c]	573761	1			T1	4		T4	9524		T5	15
valid_sources[0x6d]	525086	1			T1	8		T3	45		T5	65
valid_sources[0x6e]	1554254	1			T1	12		T4	14		T5	17
valid_sources[0x6f]	543941	1			T1	6		T5	32		T8	267
valid_sources[0x70]	756654	1			T1	5		T5	61		T8	237
valid_sources[0x71]	538410	1			T1	10		T3	59		T5	47
valid_sources[0x72]	517822	1			T1	4		T5	47		T8	259
valid_sources[0x73]	560056	1			T1	15		T5	15		T8	237
valid_sources[0x74]	564888	1			T1	5		T5	57		T8	199
valid_sources[0x75]	526975	1			T1	6		T5	19		T8	265
valid_sources[0x76]	520030	1			T1	6		T5	58		T8	255
valid_sources[0x77]	585702	1			T1	7		T5	33		T8	233
valid_sources[0x78]	552169	1			T1	11		T5	15		T8	237
valid_sources[0x79]	533073	1			T1	5		T5	51		T8	195
valid_sources[0x7a]	618639	1			T1	7		T5	44		T8	245
valid_sources[0x7b]	521419	1			T1	10		T3	47		T5	72
valid_sources[0x7c]	562292	1			T1	18		T5	31		T8	249
valid_sources[0x7d]	517516	1			T1	9		T5	17		T8	195
valid_sources[0x7e]	596854	1			T1	13		T5	43		T8	283
valid_sources[0x7f]	565265	1			T1	7		T5	32		T8	205
valid_sources[0x80]	2251446	1			T1	6		T5	30		T8	221

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

77217084

1

T1

932

T3

1285

T4

4396

values[0x0]

all_enables

biggest_size

39980336

1

T1

487

T3

593

T4

2095

values[0x1]

all_enables

biggest_size

39993100

1

T1

471

T3

598

T4

2156

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	35082	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

160888

1

T2

3

T3

24

T5

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	56429	1			T3	25		T6	76		T7	27
values[0x0]	67278	1			T2	5		T3	13		T4	1
values[0x1]	72263	1			T1	2		T2	3		T3	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	26521	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

169449

1

T1

1

T2

3

T3

27

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	701	1			T15	3		T25	3		T26	6
valid_sources[0x01]	967	1			T25	2		T26	18		T27	1
valid_sources[0x02]	700	1			T3	1		T16	1		T25	5
valid_sources[0x03]	810	1			T6	1		T25	1		T26	4
valid_sources[0x04]	764	1			T100	1		T25	4		T26	7
valid_sources[0x05]	811	1			T3	1		T6	1		T15	3
valid_sources[0x06]	1256	1			T6	1		T25	6		T26	7
valid_sources[0x07]	1202	1			T10	1		T26	23		T27	3
valid_sources[0x08]	567	1			T6	1		T25	8		T26	12
valid_sources[0x09]	703	1			T6	2		T16	1		T25	9
valid_sources[0x0a]	830	1			T95	1		T25	8		T26	21
valid_sources[0x0b]	776	1			T6	1		T16	1		T25	8
valid_sources[0x0c]	681	1			T6	1		T16	1		T25	11
valid_sources[0x0d]	913	1			T6	2		T25	8		T26	35
valid_sources[0x0e]	641	1			T20	1		T25	7		T26	7
valid_sources[0x0f]	737	1			T25	17		T26	21		T38	3
valid_sources[0x10]	658	1			T10	1		T25	16		T26	14
valid_sources[0x11]	664	1			T6	1		T25	9		T26	5
valid_sources[0x12]	628	1			T6	1		T15	1		T25	8
valid_sources[0x13]	911	1			T6	3		T16	1		T25	12
valid_sources[0x14]	683	1			T6	5		T20	1		T25	11
valid_sources[0x15]	884	1			T6	2		T25	12		T26	10
valid_sources[0x16]	672	1			T25	4		T26	25		T27	21
valid_sources[0x17]	767	1			T25	5		T26	36		T28	2
valid_sources[0x18]	906	1			T6	1		T25	10		T26	14
valid_sources[0x19]	941	1			T6	1		T100	1		T25	8
valid_sources[0x1a]	903	1			T6	2		T13	6		T25	7
valid_sources[0x1b]	847	1			T16	1		T25	4		T26	7
valid_sources[0x1c]	524	1			T16	1		T25	4		T26	5
valid_sources[0x1d]	754	1			T3	1		T16	1		T25	5
valid_sources[0x1e]	572	1			T8	1		T6	3		T81	1
valid_sources[0x1f]	627	1			T16	3		T51	5		T25	8
valid_sources[0x20]	926	1			T10	1		T6	1		T25	1
valid_sources[0x21]	735	1			T3	2		T25	10		T26	18
valid_sources[0x22]	595	1			T25	9		T48	1		T26	7
valid_sources[0x23]	747	1			T6	1		T16	2		T50	17
valid_sources[0x24]	812	1			T25	12		T26	35		T52	2
valid_sources[0x25]	592	1			T25	5		T26	19		T28	1
valid_sources[0x26]	509	1			T11	2		T25	4		T26	5
valid_sources[0x27]	708	1			T6	1		T25	7		T48	1
valid_sources[0x28]	869	1			T25	3		T26	6		T28	1
valid_sources[0x29]	611	1			T15	2		T25	7		T26	21
valid_sources[0x2a]	1133	1			T25	7		T17	7		T26	16
valid_sources[0x2b]	1229	1			T6	1		T25	5		T26	13
valid_sources[0x2c]	682	1			T6	1		T25	5		T26	2
valid_sources[0x2d]	857	1			T6	4		T16	1		T25	5
valid_sources[0x2e]	761	1			T5	1		T6	3		T25	5
valid_sources[0x2f]	660	1			T10	1		T6	1		T11	1
valid_sources[0x30]	579	1			T25	2		T26	6		T27	8
valid_sources[0x31]	969	1			T15	3		T25	4		T26	6
valid_sources[0x32]	810	1			T13	1		T25	8		T26	11
valid_sources[0x33]	1075	1			T6	1		T7	13		T25	5
valid_sources[0x34]	519	1			T6	2		T25	9		T26	9
valid_sources[0x35]	596	1			T2	3		T3	1		T25	6
valid_sources[0x36]	722	1			T26	13		T28	1		T27	3
valid_sources[0x37]	893	1			T6	1		T7	1		T11	4
valid_sources[0x38]	685	1			T6	1		T16	2		T25	3
valid_sources[0x39]	1232	1			T25	8		T26	21		T43	9
valid_sources[0x3a]	774	1			T6	1		T25	4		T26	34
valid_sources[0x3b]	557	1			T25	5		T49	1		T26	25
valid_sources[0x3c]	1139	1			T25	3		T49	5		T26	2
valid_sources[0x3d]	975	1			T6	1		T25	5		T26	16
valid_sources[0x3e]	613	1			T25	5		T26	15		T27	16
valid_sources[0x3f]	919	1			T6	3		T16	1		T25	8
valid_sources[0x40]	627	1			T6	1		T25	14		T34	1
valid_sources[0x41]	956	1			T3	1		T25	10		T26	9
valid_sources[0x42]	848	1			T6	1		T25	8		T26	4
valid_sources[0x43]	714	1			T6	2		T51	4		T25	12
valid_sources[0x44]	613	1			T6	1		T15	2		T25	3
valid_sources[0x45]	655	1			T3	1		T6	2		T16	1
valid_sources[0x46]	560	1			T6	1		T25	7		T26	13
valid_sources[0x47]	909	1			T25	7		T26	6		T28	1
valid_sources[0x48]	626	1			T6	2		T25	14		T49	3
valid_sources[0x49]	576	1			T6	3		T25	6		T26	18
valid_sources[0x4a]	711	1			T6	2		T7	1		T69	37
valid_sources[0x4b]	661	1			T3	1		T25	3		T26	23
valid_sources[0x4c]	694	1			T6	1		T25	3		T26	3
valid_sources[0x4d]	918	1			T6	1		T15	2		T25	11
valid_sources[0x4e]	760	1			T6	2		T7	1		T25	5
valid_sources[0x4f]	755	1			T6	2		T25	13		T26	19
valid_sources[0x50]	570	1			T25	6		T26	10		T28	1
valid_sources[0x51]	647	1			T3	1		T6	1		T25	1
valid_sources[0x52]	748	1			T1	2		T2	1		T10	1
valid_sources[0x53]	961	1			T25	6		T26	6		T96	4
valid_sources[0x54]	998	1			T3	1		T6	1		T25	1
valid_sources[0x55]	758	1			T16	1		T25	3		T26	25
valid_sources[0x56]	821	1			T6	1		T14	203		T25	13
valid_sources[0x57]	523	1			T6	2		T25	10		T26	20
valid_sources[0x58]	792	1			T6	1		T16	1		T25	10
valid_sources[0x59]	1128	1			T6	1		T25	7		T26	10
valid_sources[0x5a]	1114	1			T6	2		T7	3		T83	1
valid_sources[0x5b]	702	1			T6	2		T11	9		T25	10
valid_sources[0x5c]	583	1			T6	2		T25	14		T26	21
valid_sources[0x5d]	697	1			T10	1		T25	8		T26	14
valid_sources[0x5e]	948	1			T6	1		T16	1		T25	5
valid_sources[0x5f]	935	1			T6	2		T7	6		T16	1
valid_sources[0x60]	666	1			T6	1		T15	2		T26	7
valid_sources[0x61]	834	1			T6	2		T25	6		T17	8
valid_sources[0x62]	650	1			T25	4		T26	26		T43	14
valid_sources[0x63]	578	1			T25	22		T26	13		T27	3
valid_sources[0x64]	1025	1			T6	2		T40	3		T25	10
valid_sources[0x65]	652	1			T2	2		T15	1		T16	1
valid_sources[0x66]	594	1			T3	1		T16	1		T25	6
valid_sources[0x67]	844	1			T6	1		T25	1		T26	4
valid_sources[0x68]	702	1			T16	1		T25	5		T26	34
valid_sources[0x69]	681	1			T25	8		T26	24		T39	2
valid_sources[0x6a]	924	1			T3	2		T25	13		T26	16
valid_sources[0x6b]	561	1			T3	1		T25	12		T26	19
valid_sources[0x6c]	603	1			T13	1		T25	5		T26	31
valid_sources[0x6d]	727	1			T25	2		T26	18		T52	1
valid_sources[0x6e]	822	1			T3	1		T25	3		T26	16
valid_sources[0x6f]	769	1			T6	2		T25	7		T26	4
valid_sources[0x70]	638	1			T3	1		T25	4		T26	22
valid_sources[0x71]	1070	1			T3	1		T89	1		T100	1
valid_sources[0x72]	954	1			T16	3		T25	8		T26	12
valid_sources[0x73]	583	1			T7	5		T25	4		T26	30
valid_sources[0x74]	631	1			T11	2		T25	5		T26	14
valid_sources[0x75]	790	1			T6	2		T100	1		T25	3
valid_sources[0x76]	751	1			T16	1		T25	15		T26	21
valid_sources[0x77]	685	1			T6	1		T16	1		T25	12
valid_sources[0x78]	609	1			T3	1		T6	1		T16	1
valid_sources[0x79]	576	1			T6	1		T15	4		T95	1
valid_sources[0x7a]	719	1			T11	3		T15	2		T25	15
valid_sources[0x7b]	590	1			T6	1		T15	1		T25	8
valid_sources[0x7c]	611	1			T3	1		T6	1		T25	9
valid_sources[0x7d]	778	1			T6	1		T25	10		T26	23
valid_sources[0x7e]	641	1			T6	1		T33	2		T26	13
valid_sources[0x7f]	636	1			T25	5		T26	17		T52	1
valid_sources[0x80]	618	1			T25	1		T37	2		T26	22

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

43717

1

T3

14

T6

32

T7

16

values[0x0]

all_enables

biggest_size

59218

1

T2

3

T3

8

T8

1

values[0x1]

all_enables

biggest_size

57953

1

T3

2

T5

1

T10

1