Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[sram_ctrl_prim_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

15998335

1

T1

402

T3

9

T4

891

full_word

154132489

1

T1

1890

T3

184

T4

8647

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	170130534	1			T1	2292		T3	193		T4	9538
auto[TlIntgErrCmd]	91	1			T97	1		T98	7		T99	3
auto[TlIntgErrData]	98	1			T97	13		T98	1		T99	4
auto[TlIntgErrBoth]	101	1			T97	6		T98	2		T99	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

82062898

1

T1

1125

T3

92

T4

4869

auto[1]

88067926

1

T1

1167

T3

101

T4

4669

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	7830463	1			T1	193		T3	5		T4	473
auto[TlIntgErrNone]	partial	auto[1]	8167609	1			T1	209		T3	4		T4	418
auto[TlIntgErrNone]	full_word	auto[0]	74232287	1			T1	932		T3	87		T4	4396
auto[TlIntgErrNone]	full_word	auto[1]	79900175	1			T1	958		T3	97		T4	4251
auto[TlIntgErrCmd]	partial	auto[0]	36	1			T98	2		T99	2		T112	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T98	4		T99	1		T111	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T97	1		T115	1		T120	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1			T98	1		T111	1		T112	1
auto[TlIntgErrData]	partial	auto[0]	48	1			T97	5		T99	2		T111	4
auto[TlIntgErrData]	partial	auto[1]	40	1			T97	6		T98	1		T99	2
auto[TlIntgErrData]	full_word	auto[0]	6	1			T97	1		T112	1		T113	1
auto[TlIntgErrData]	full_word	auto[1]	4	1			T97	1		T117	1		T116	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T97	2		T98	2		T99	3
auto[TlIntgErrBoth]	partial	auto[1]	39	1			T97	3		T111	3		T112	1
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T121	1		T122	1		T118	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1			T97	1		T115	1		T116	1