Unified Coverage Report :: Group :: mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

Group : mem_bkdr_scb_pkg::mem_bkdr_scb#(32,32)::b2b_access_types_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_mem_bkdr_scb_0/mem_bkdr_scb.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mem_bkdr_scb	100.00	1	100	1	64	64

---

Group Instance : mem_bkdr_scb

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mem_bkdr_scb

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	32	0	32	100.00

Variables for Group Instance mem_bkdr_scb

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
b2b_access_types_cp	4	0	4	100.00	100	1	1	4
b2b_partial_types_cp	4	0	4	100.00	100	1	1	4
raw_hazard_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance mem_bkdr_scb

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
all_cross	32	0	32	100.00	100	1	1	0

Summary for Variable b2b_access_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_access_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	903362	1			T3	25		T8	8910		T10	1351
auto[1]	10365069	1			T1	1125		T3	1		T4	11
auto[2]	704845	1			T3	15		T8	6652		T10	570
auto[3]	10090362	1			T1	1166		T3	2		T4	17

---

Summary for Variable b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for b2b_partial_types_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	13918868	1			T1	1581		T3	37		T4	22
auto[1]	2018194	1			T1	308		T3	4		T4	2
auto[2]	2035060	1			T1	334		T3	2		T4	3
auto[3]	4091516	1			T1	68		T4	1		T5	3

---

Summary for Variable raw_hazard_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for raw_hazard_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

10257242

1

T1

2291

T3

43

T4

28

auto[1]

11806396

1

T8

4

T15

3

T40

166194

---

Summary for Cross all_cross

Samples crossed: raw_hazard_cp b2b_access_types_cp b2b_partial_types_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for all_cross

Bins

raw_hazard_cp	b2b_access_types_cp	b2b_partial_types_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	364538	1			T3	23		T8	1		T10	1088
auto[0]	auto[0]	auto[1]	38640	1			T3	1		T8	76		T10	125
auto[0]	auto[0]	auto[2]	38432	1			T3	1		T8	88		T10	127
auto[0]	auto[0]	auto[3]	164597	1			T8	8741		T10	11		T14	61
auto[0]	auto[1]	auto[0]	3447531	1			T1	793		T3	1		T4	8
auto[0]	auto[1]	auto[1]	373179	1			T1	139		T4	1		T8	77
auto[0]	auto[1]	auto[2]	381341	1			T1	164		T4	1		T8	120
auto[0]	auto[1]	auto[3]	505901	1			T1	29		T4	1		T5	2
auto[0]	auto[2]	auto[0]	276062	1			T3	12		T8	5		T10	444
auto[0]	auto[2]	auto[1]	40842	1			T3	3		T8	708		T10	40
auto[0]	auto[2]	auto[2]	26499	1			T8	58		T10	77		T6	1
auto[0]	auto[2]	auto[3]	113497	1			T8	5881		T10	9		T14	76
auto[0]	auto[3]	auto[0]	3298164	1			T1	788		T3	1		T4	14
auto[0]	auto[3]	auto[1]	361588	1			T1	169		T4	1		T8	56
auto[0]	auto[3]	auto[2]	387991	1			T1	170		T3	1		T4	2
auto[0]	auto[3]	auto[3]	438440	1			T1	39		T5	1		T8	5819
auto[1]	auto[0]	auto[0]	9939	1			T89	947		T90	1007		T91	602
auto[1]	auto[0]	auto[1]	44340	1			T8	1		T89	4197		T90	4599
auto[1]	auto[0]	auto[2]	43801	1			T89	4209		T90	4569		T91	2684
auto[1]	auto[0]	auto[3]	199075	1			T8	3		T89	18783		T90	20271
auto[1]	auto[1]	auto[0]	3259437	1			T15	1		T40	69153		T16	3
auto[1]	auto[1]	auto[1]	582358	1			T40	6271		T16	1		T89	4202
auto[1]	auto[1]	auto[2]	546640	1			T40	6764		T89	717		T35	6355
auto[1]	auto[1]	auto[3]	1268682	1			T40	648		T89	18954		T35	583
auto[1]	auto[2]	auto[0]	8324	1			T89	871		T90	952		T91	514
auto[1]	auto[2]	auto[1]	36900	1			T89	3921		T90	4167		T91	2466
auto[1]	auto[2]	auto[2]	36825	1			T89	2803		T90	3123		T91	2285
auto[1]	auto[2]	auto[3]	165896	1			T89	12557		T90	13643		T91	10566
auto[1]	auto[3]	auto[0]	3254873	1			T15	2		T40	69324		T16	1
auto[1]	auto[3]	auto[1]	540347	1			T40	7031		T89	393		T35	6082
auto[1]	auto[3]	auto[2]	573531	1			T40	6372		T89	2774		T35	5582
auto[1]	auto[3]	auto[3]	1235428	1			T40	631		T16	1		T89	12991